Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

Abstract: In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.

Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: A silicon nitride film is formed above a semiconductor substrate so as to cover a gate electrode. Next, a silicon thermal oxidation film is formed on the surface of the silicon nitride film by carrying out thermal oxidation processing on the silicon nitride film. In the case that a pinhole exists in the silicon nitride film, the inside of the pinhole is also oxidized so as to be filled in with the silicon thermal oxidation film. Next, a silicon nitride film is formed by carrying out anisotropic etching on the silicon nitride film. After that, a contact hole is formed in the silicon oxide film, which is formed above the semiconductor substrate. A bit line contact part is formed within the contact hole and, then, a bit line is formed. Thereby, a semiconductor device is gained wherein an electrical short circuit can be prevented.

Abstract: A method of producing a semiconductor memory having a memory cell structure in which a storage node, which consists of a capacitor electrode film having a rugged surface formed inside holes of an interlayer insulating film that is deposited on a substrate, constitutes a capacitor together with a cell plate through a dielectric film.

Abstract: A method of producing a semiconductor memory having a memory cell structure in which a storage node, which consists of a capacitor electrode film having a rugged surface formed inside holes of an interlayer insulating film that is deposited on a substrate, constitutes a capacitor together with a cell plate through a dielectric film.

Abstract: A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film (21) formed of p-TEOS is deposited to cover a substrate (1) and wires (4) formed on the substrate (1). A second insulation film (22) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate (1); therefore, the second insulation film (22) is etched. The etching is stopped at the point where the surface (21a) of the first insulation film (21) on the wires (4) is exposed. This ensures good surface,planarity. A third insulation film (23) is stacked on top of the second insulation film (22), and portions of the third insulation film (23) above the wires (4) are isotropically etched to form openings (51). At this time, the isotropic etching does not extend over the second insulation film (22).

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (12) in which impurity is diffused is deposited on the entire surface including the inside of a hole (8A). An etching process of the polysilicon layer (12) is performed to form a storage node electrode composed of the polysilicon layer (12) remaining on the bottom and side of a groove for metallization (15) and in the hole (8A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (15), and a plug part disposed in the hole (8A). The storage node electrode is electrically connected via the plug part to a diffused region (19) of a semiconductor substrate (1).

Abstract: There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC.