Patents by Inventor Akinori Matsuo

Akinori Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190367776
    Abstract: A polishing liquid is provided containing manganese oxide abrasive grains, permanganate ions, and a cellulosic surfactant or a cationic surfactant. The polishing liquid has a pH of 5 or more and 11 or less. The cellulosic surfactant is preferably a carboxymethyl cellulose or a derivative thereof. The cationic surfactant preferably has a quaternary ammonium ion site. The content of the cellulosic surfactant or the cationic surfactant is preferably 0.01 mass % or more and 1.0 mass % or less based on the total amount of the polishing liquid.
    Type: Application
    Filed: August 15, 2017
    Publication date: December 5, 2019
    Inventors: Ken MATSUO, Masayuki MATSUYAMA, Mikimasa HORIUCHI, Akinori KUMAGAI
  • Patent number: 7336535
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 26, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Publication number: 20070171692
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: March 28, 2007
    Publication date: July 26, 2007
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Patent number: 7212425
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: May 1, 2007
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Patent number: 7002830
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: February 21, 2006
    Assignees: Renesas Technology Corp., Hitachi VLSI Engineering Corp.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Publication number: 20060018172
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: September 19, 2005
    Publication date: January 26, 2006
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Patent number: 6751138
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: June 15, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Publication number: 20040090838
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: October 28, 2003
    Publication date: May 13, 2004
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Publication number: 20030095434
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: November 21, 2002
    Publication date: May 22, 2003
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Patent number: 6501689
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: December 31, 2002
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Publication number: 20020048204
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: October 25, 2001
    Publication date: April 25, 2002
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Patent number: 6064606
    Abstract: A nonvolatile storage element of single-layer gate structure constructed by arranging a floating gate formed of a conductive layer to partly overlap with a control gate formed of a diffused layer is provided with a barrier layer covering a part or the whole of the surface of the floating gate. Such nonvolatile storage elements are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: May 16, 2000
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Patent number: 5994732
    Abstract: A nonvolatile semiconductor memory device has a plurality of p well regions in a memory cell array region. P well region is independently provided for each erase block. Each p well region is connected to a common well/source line driver, respectively. Well/source line driver is connected to a well/source power supply and a well/block decoder. Therefore, a nonvolatile semiconductor memory device which can inhibit a well disturbance in erase operation can be provided.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: November 30, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Hitachi, Ltd., Hitachi Ulsi Engineering Corp.
    Inventors: Natsuo Ajika, Akinori Matsuo
  • Patent number: 5896317
    Abstract: It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: April 20, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Motoharu Ishii, Shinichi Kobayashi, Akinori Matsuo, Masashi Wada
  • Patent number: 5852583
    Abstract: Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.
    Type: Grant
    Filed: May 8, 1997
    Date of Patent: December 22, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuhiko Taito, Shinji Kawai, Shinichi Kobayashi, Akinori Matsuo, Masashi Wada
  • Patent number: 5847995
    Abstract: The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: December 8, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Kobayashi, Shinji Kawai, Tadashi Omae, Makoto Oi, Akinori Matsuo, Masashi Wada, Kenji Kozakai
  • Patent number: 5767544
    Abstract: A nonvolatile storage element of single-layer gate structure constructed by arranging a floating gate formed of a conductive layer to partly overlap with a control gate formed of a diffused layer is provided with a barrier layer covering a part or the whole of the surface of the floating gate. Such nonvolatile storage elements are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 16, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Patent number: 5747849
    Abstract: A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulately above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate.
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: May 5, 1998
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Kenichi Kuroda, Kazuyoshi Shiba, Akinori Matsuo
  • Patent number: 5615151
    Abstract: Any one of the internal circuits of a semiconductor integrated circuit is made to operate both at a relatively high operating voltage having a predetermined allowable range and at a relatively low operating voltage also having a predetermined allowable range. The operating voltage is supplied from the outside. Moreover, the operating conditions of the internal circuits constituting the semiconductor integrated circuit are individually set restrictive to the relatively high operating voltage having a predetermined allowable range and to the relatively low operating voltage having a predetermined allowable range. The semiconductor integrated circuit is made to operate selectively at these operating voltages. Since the internal circuits are operated at these two kinds of operating voltages, an arrangement of internal circuits can be simplified and at the same time the semiconductor integrated circuit is usable in not only the conventional system but also a low-voltage one.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 25, 1997
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takeshi Furuno, Yasuhiro Nakamura, Akinori Matsuo
  • Patent number: 5548146
    Abstract: A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulatedly above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 20, 1996
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Kenichi Kuroda, Kazuyoshi Shiba, Akinori Matsuo