Patents by Inventor Akinori Matsuo
Akinori Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240310343Abstract: Provided is a novel space evaluation system capable of simply and quantitatively evaluating how close an unknown space is to a natural environment. The space evaluation system 1 comprises: a setting unit 12 for setting naturalness as an index of how close a space is to a natural environment; and an estimating unit 11 for estimating, from air quality data indicating a type of material including a microbe included in a sample collected from air in a target space to be evaluated and indicating an abundance of each material, the naturalness of the target space from which the sample has been collected.Type: ApplicationFiled: January 14, 2022Publication date: September 19, 2024Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION RESEARCH ORGANIZATION OF INFORMATION AND SYSTEMSInventors: Akinobu TOYODA, Masakazu ITO, Satoshi KATAHIRA, Yuji MATSUO, Akinori IKEUCHI, Ken KUROKAWA, Koichi HIGASHI, Hiroshi MORI
-
Patent number: 7336535Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: March 28, 2007Date of Patent: February 26, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Publication number: 20070171692Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: March 28, 2007Publication date: July 26, 2007Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Patent number: 7212425Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: September 19, 2005Date of Patent: May 1, 2007Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Patent number: 7002830Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: October 28, 2003Date of Patent: February 21, 2006Assignees: Renesas Technology Corp., Hitachi VLSI Engineering Corp.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Publication number: 20060018172Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: September 19, 2005Publication date: January 26, 2006Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Patent number: 6751138Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: November 21, 2002Date of Patent: June 15, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Publication number: 20040090838Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: October 28, 2003Publication date: May 13, 2004Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Publication number: 20030095434Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: November 21, 2002Publication date: May 22, 2003Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Patent number: 6501689Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: October 25, 2001Date of Patent: December 31, 2002Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Publication number: 20020048204Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: October 25, 2001Publication date: April 25, 2002Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Patent number: 6064606Abstract: A nonvolatile storage element of single-layer gate structure constructed by arranging a floating gate formed of a conductive layer to partly overlap with a control gate formed of a diffused layer is provided with a barrier layer covering a part or the whole of the surface of the floating gate. Such nonvolatile storage elements are used for redundancy control of defects or change of functions.Type: GrantFiled: December 31, 1997Date of Patent: May 16, 2000Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Patent number: 5994732Abstract: A nonvolatile semiconductor memory device has a plurality of p well regions in a memory cell array region. P well region is independently provided for each erase block. Each p well region is connected to a common well/source line driver, respectively. Well/source line driver is connected to a well/source power supply and a well/block decoder. Therefore, a nonvolatile semiconductor memory device which can inhibit a well disturbance in erase operation can be provided.Type: GrantFiled: May 7, 1997Date of Patent: November 30, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Hitachi, Ltd., Hitachi Ulsi Engineering Corp.Inventors: Natsuo Ajika, Akinori Matsuo
-
Patent number: 5896317Abstract: It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.Type: GrantFiled: May 7, 1997Date of Patent: April 20, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Motoharu Ishii, Shinichi Kobayashi, Akinori Matsuo, Masashi Wada
-
Patent number: 5852583Abstract: Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.Type: GrantFiled: May 8, 1997Date of Patent: December 22, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuhiko Taito, Shinji Kawai, Shinichi Kobayashi, Akinori Matsuo, Masashi Wada
-
Patent number: 5847995Abstract: The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.Type: GrantFiled: May 7, 1997Date of Patent: December 8, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shinichi Kobayashi, Shinji Kawai, Tadashi Omae, Makoto Oi, Akinori Matsuo, Masashi Wada, Kenji Kozakai
-
Patent number: 5767544Abstract: A nonvolatile storage element of single-layer gate structure constructed by arranging a floating gate formed of a conductive layer to partly overlap with a control gate formed of a diffused layer is provided with a barrier layer covering a part or the whole of the surface of the floating gate. Such nonvolatile storage elements are used for redundancy control of defects or change of functions.Type: GrantFiled: June 6, 1995Date of Patent: June 16, 1998Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
-
Patent number: 5747849Abstract: A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulately above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate.Type: GrantFiled: June 25, 1996Date of Patent: May 5, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Kenichi Kuroda, Kazuyoshi Shiba, Akinori Matsuo
-
Patent number: 5615151Abstract: Any one of the internal circuits of a semiconductor integrated circuit is made to operate both at a relatively high operating voltage having a predetermined allowable range and at a relatively low operating voltage also having a predetermined allowable range. The operating voltage is supplied from the outside. Moreover, the operating conditions of the internal circuits constituting the semiconductor integrated circuit are individually set restrictive to the relatively high operating voltage having a predetermined allowable range and to the relatively low operating voltage having a predetermined allowable range. The semiconductor integrated circuit is made to operate selectively at these operating voltages. Since the internal circuits are operated at these two kinds of operating voltages, an arrangement of internal circuits can be simplified and at the same time the semiconductor integrated circuit is usable in not only the conventional system but also a low-voltage one.Type: GrantFiled: June 7, 1995Date of Patent: March 25, 1997Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Takeshi Furuno, Yasuhiro Nakamura, Akinori Matsuo
-
Patent number: 5548146Abstract: A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulatedly above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate.Type: GrantFiled: June 6, 1995Date of Patent: August 20, 1996Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Kenichi Kuroda, Kazuyoshi Shiba, Akinori Matsuo