Abstract: A service level agreement (SLA) monitoring system is provided for making fair determination as to an extent to which an SLA is achieved and for facilitating a procedure taken by a user to receive compensation when the SLA is violated. The monitoring system comprises a plurality of service level probing boxes and a monitoring center. Each of the service level probing boxes, which is installed as an interface between each user network and a provider network, monitors user packets to detect whether the SLA is violated, when the user packets flow from an originating user network to the provider network and when the user packets flow from the provider network to a destination user network, and transmits the result of detection to the monitoring center. The monitoring center conducts fact finding for a violation of the SLA based on information from each of the service level probing boxes, and acts as a procedure for claiming compensation in the name of a user in conformity with an SLA contract.

Abstract: A service level agreement (SLA) monitoring system is provided for making fair determination as to an extent to which an SLA is achieved and for facilitating a procedure taken by a user to receive compensation when the SLA is violated. The monitoring system comprises a plurality of service level probing boxes and a monitoring center. Each of the service level probing boxes, which is installed as an interface between each user network and a provider network, monitors user packets to detect whether the SLA is violated, when the user packets flow from an originating user network to the provider network and when the user packets flow from the provider network to a destination user network, and transmits the result of detection to the monitoring center. The monitoring center conducts fact finding for a violation of the SLA based on information from each of the service level probing boxes, and acts as a procedure for claiming compensation in the name of a user in conformity with an SLA contract.

Abstract: An integrated circuit has a data transfer system which is simple in switching control and timing extraction of transfer. A bus provided between four modules has a bit width the same as number of bits consisting a transfer data. The bus is divided into a plurality of fractions respectively lying between a plurality of modules. Respective divided fractions are connected by adapters. The adapter includes a lip-flip or the like temporarily holds data to be transmitted from one fraction of the transmission path and outputs to another fraction of the transmission path to form a ring transmission path. Since data flows in a predetermined direction on the bus, control can be simple. Also, since a plurality of modules can perform transmission and reception of data at the same timing, transfer efficiency can be improved significantly.

Abstract: An entry storing packet information to be retrieved at a high speed is hit by retrieval with a high-speed retrieval mechanism. Packet information to be retrieved at a medium speed is not cataloged in the high-speed retrieval mechanism and is miss-hit by retrieval with the high-speed retrieval mechanism, but is hit by retrieval with a medium-speed retrieval mechanism. The other packet information is cataloged in only a low-speed retrieval mechanism, which is realized by software or the like, and is hit by retrieval with the low-speed retrieval mechanism. This construction can realize a table-type data retrieval mechanism which can realize required retrieval performance at low cost and can dynamically cope with a variation in packet arrival frequency to reduce unnecessary cost.

Abstract: A transfer control table contains a source memory designation field, a desired region designation field, a shifting amount designation field, and a destination memory designation field. An source selection circuit selects source designation word data from the source word data stored in the source memory according to source memory designation data contained in the source memory designation field to provide the source designation word data. A transfer data bit operation circuit extracts, in response to the source designation word data, only the word data required for transfer as valid word data according to desired region designation data contained in the desired region designation field to shift the valid word data by a bit width that is predetermined based on shifting amount designation data contained in the shifting amount designation field and then to provide the shifted valid word data.

Abstract: A fetching apparatus (20) is for use in a data processing equipment comprising a processor (11) and a main memory (12). The main memory has a page structure comprising a plurality of pages each of which has a plurality of page data. The fetching apparatus is located between the processor and the main memory. The fetching apparatus fetches the page data of a specific one of the pages as fetched page data from the main memory and supplies the fetched page data to said processor. The fetching apparatus comprises a plurality of registers (23-1 to 23-K) each of which is for memorizing the fetched page data. A table section (24) is for memorizing addresses corresponding the page data in each of the page. The table section further memorizes, as data transfer locations, the memory areas corresponding to the addresses.

Abstract: In order to buffer a succession of input data sets to produce a succession of output data sets, an input/output buffer memory circuit includes a plurality of internal memory elements (1), each having a memory capacity capable of memorizing each of the input data sets. An input port (2) and an input control circuit (3) write each of the input data sets in any one of the internal memory elements as an internal data set. At least one random access port (4) carries out a random access to any one of the internal memory elements to subject the internal data set of any one of the internal memory elements to an internal data processing as a processed data set. An output control circuit (6) reads the processed data set out of any one of the internal memory elements and delivers the read data set to an output port (5) as each of the output data sets.