Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

Abstract: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

Abstract: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

Abstract: In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.

Abstract: During probe testing using a prober having probe needles formed by using a manufacturing technology for a semiconductor integrated circuit device, reliable contact is ensured between the probe needles and test pads. A pressing tool having at least one hole portion formed therein and extending therethrough between the main and back surface thereof is prepared. An elastomer in the form of a sheet and a polyimide sheet are successively disposed on the main surface of the pressing tool. With th elastomer and the polyimide sheet being electrostatically attracted to the pressing tool, the pressing tool is disposed on a thin-film sheet such that the main surface thereof faces the back surface (the surface opposite to the main surface thereof formed with the probe) of the thin-film sheet. Then, the thin-film sheet with the pressing tool bonded thereto is attached to a probe card.

Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Abstract: A probe card has first contact terminals electrically connected to the fine-pitch electrodes of a test target; wirings drawn from the first contact terminals; and second contact terminals electrically connected to the wirings, wherein the first contact terminals are formed each using an anisotropically etched hole in a crystalline substrate, and a semiconductor device test method (fabrication method) using the probe card.

Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.

Abstract: In the connecting apparatus for inspecting the semiconductor chip, in which contact terminals are electrically connected to each of the plurality of electrode pads formed on the semiconductor chips, a part of metal projections in the shape of quadrangular pyramid which constitute the contact terminals is composed of insulator in the present invention. Therefore, the inspection of semiconductor chips performed by simultaneously transmitting high-speed signals to the plurality of minute electrode pads arranged at a narrow pitch on the semiconductor chips can be realized.

Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A probing device for electrically contacting with a plurality of electrodes 3, 6 aligned on an object 1 to be tested so as to transfer electrical signal therewith, comprising: a wiring sheet being formed by aligning a plurality of contact electrodes 21, 110b, corresponding to each of said electrodes, each being planted with projecting probes 20, 110a covered with hard metal films on basis of a conductor thin film 41 formed on one surface of an insulator sheet 22 of a polyimide film by etching thereof, while extension wiring 23, 110c for electrically connecting to said each of said contact electrodes being formed on basis of a conductor thin film formed on either said one surface or the other surface opposing thereto of said insulator sheet of the polyimide film; and means for giving contacting pressure for obtaining electrical conduction between said extension wiring and said object to be tested by contacting tips of said projecting contact probe formed onto said each contact electrode through giving pressuri

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Abstract: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.