Patents by Inventor Akio Hirayama

Akio Hirayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240181435
    Abstract: Provided is a molded catalyst serving as a methanation catalyst that supports ruthenium as an activated metal, and has high activity at low temperatures, sufficient strength for industrial use, and heat resistance under high temperature and high water vapor pressure conditions. Provided is a carbon dioxide methanation catalyst molded body including an activated alumina molded body, and zirconia and ruthenium supported on the activated alumina molded body, in which the amount of zirconia supported is 3 to 10 parts by mass with respect to 100 parts by mass of the activated alumina molded body, the amount of ruthenium supported is 0.1 to 5 parts by mass per 100 parts by mass of the activated alumina molded body, and the carbon dioxide methanation catalyst molded body is a molded body having a particle diameter of 2 to 20 mm.
    Type: Application
    Filed: April 20, 2022
    Publication date: June 6, 2024
    Inventors: Hirofumi Ohtsuka, Shimpei Norioka, Akio Hirayama
  • Patent number: 6253354
    Abstract: In a method and apparatus of the present invention, variations in source voltage of the power source wiring of an LSI are analyzed cell by cell without test patterns. An operation time calculator (14) statically calculates the operation time of each instance of a given logic circuit according to the outputs of a net list unit (11), a layout data unit (12), and a cell delay library (13). A maximum current calculator (16) calculates the time, value, and location of maximum current consumption of the logic circuit as a whole according to the outputs of operation time calculator (14), net list unit (11), layout data unit (12); and a cell power library (15). A variation analyzer (17) analyzes and verifies a voltage drop in the power source wiring of the logic circuit according to the output of the maximum current calculator (16).
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: June 26, 2001
    Assignee: Fujitsu Limited
    Inventors: Kazusumi Kuwano, Akio Hirayama