Patents by Inventor Akio Hosokawa

Akio Hosokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150215575
    Abstract: A relay apparatus (10) is provided with a first signal transmitting device compliant with one second signal transmitting device compliant with another standard, a first obtaining device, a second obtaining device, a generating device and a controlling device. If the relay apparatus is connected to an output apparatus via the first signal transmitting device and is connected to a first unit via the second signal transmitting device, the first obtaining device obtains first information about the first unit; a second obtaining device obtains second information about a second unit connected to the output apparatus; a generating device generates third information that allows selection and operation of each of first and second units, on the basis of first and second information, and transmits the third information to the output apparatus; and a controlling device controls the first unit according to a command signal outputted from the output apparatus.
    Type: Application
    Filed: May 11, 2012
    Publication date: July 30, 2015
    Applicant: Pioneer Digital Design and Manufacturing Corporation
    Inventors: Yasuhiro Rin, Mamoru Oda, Takeshi Hashimoto, Yukitaka Shimizu, Satoshi Saito, Shinichiro Kinoshita, Tomoo Nishigaki, Akio Hosokawa
  • Patent number: 8421727
    Abstract: A transmitter circuit includes a driver circuit including a non-inverting output terminal and an inverting output terminal for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting output terminal and the inverting output terminal and an output-waveform control circuit for detecting a waveform edge of the input signal and responding by increasing the signal current temporarily. The output-waveform control circuit includes a first inverter circuit receiving a non-inverted input signal, a first capacitor including one end connected to an output terminal of the first inverter circuit and another end connected to the inverting output terminal, a second inverter circuit receiving an inverted input signal, and a second capacitor including one end connected to an output terminal of the second inverter circuit and another end connected to the non-inverting output terminal.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hosokawa, Kouichi Nishimura
  • Publication number: 20120188214
    Abstract: A transmitter circuit includes a driver circuit including a non-inverting output terminal and an inverting output terminal for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting output terminal and the inverting output terminal and an output-waveform control circuit for detecting a waveform edge of the input signal and responding by increasing the signal current temporarily. The output-waveform control circuit includes a first inverter circuit receiving a non-inverted input signal, a first capacitor including one end connected to an output terminal of the first inverter circuit and another end connected to the inverting output terminal, a second inverter circuit receiving an inverted input signal, and a second capacitor including one end connected to an output terminal of the second inverter circuit and another end connected to the non-inverting output terminal.
    Type: Application
    Filed: March 30, 2012
    Publication date: July 26, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Akio Hosokawa, Kouichi NISHIMURA
  • Patent number: 7394292
    Abstract: A signal transmission circuit is formed by a transmitter, a receiver, a transmission line therebetween, and a bias circuit. The transmitter receives an input signal to transmit a signal corresponding to the input signal to the input of the transmission line. A voltage amplitude of the transmitted signal is smaller than a voltage amplitude defined by first and second power supply terminals. The receiver receives the transmitted signal, adjusts a voltage of the received signal in accordance with a bias voltage to generate a voltage adjusted signal, and wave-shapes the voltage adjusted signal to generate an output signal. The bias circuit differentially amplifies the output signal of the receiver and an inverted signal thereof to generate the bias voltage. The bias circuit includes a capacitor charged and discharged in accordance with the bias voltage.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: July 1, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Akio Hosokawa, Masayuki Yamaguchi
  • Publication number: 20040242171
    Abstract: A transmitter circuit for use in a display device of the type having a transmission line consisting of aluminum or copper conductor formed on a glass substrate includes a driver circuit, which has a non-inverting output terminal and an inverting output terminal, for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting and inverting output terminals; and an output-waveform control circuit for detecting the edge of the waveform of the input signal and responding by increasing the signal current temporarily.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 2, 2004
    Applicant: NEC Electronics Corporation
    Inventors: Akio Hosokawa, Kouichi Nishimura
  • Publication number: 20040239662
    Abstract: A signal transmission circuit is formed by a transmitter, a receiver, a transmission line therebetween, and a bias circuit. The transmitter receives an input signal to transmit a signal corresponding to the input signal to the input of the transmission line. A voltage amplitude of the transmitted signal is smaller than a voltage amplitude defined by first and second power supply terminals. The receiver receives the transmitted signal, adjusts a voltage of the received signal in accordance with a bias voltage to generate a voltage adjusted signal, and wave-shapes the voltage adjusted signal to generate an output signal. The bias circuit differentially amplifies the output signal of the receiver and an inverted signal thereof to generate the bias voltage. The bias circuit includes a capacitor charged and discharged in accordance with the bias voltage.
    Type: Application
    Filed: April 15, 2004
    Publication date: December 2, 2004
    Applicant: NEC Electronics Corporation
    Inventors: Akio Hosokawa, Masayuki Yamaguchi
  • Patent number: 6605933
    Abstract: A semiconductor device including: a load connected between outputs of power amplifiers; a mirror current generating circuit connected to the power amplifiers in an output side of the power amplifiers for generating a mirror current which is smaller than and proportional to a load current applied to the load, and the mirror current generating circuit being connected out of a current path through the load between the outputs of the power amplifiers; and a mirror current detecting circuit connected to the mirror current generating circuit for detecting the mirror current.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: August 12, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Akio Hosokawa
  • Publication number: 20020109548
    Abstract: A power amplifying circuit according to the invention is provided with a first predriver that amplifies input voltage and outputs first driving voltage and second driving voltage lower than the first driving voltage, a second predriver that amplifies the input voltage and outputs third driving voltage and fourth driving voltage higher than the third driving voltage, a first push-pull output circuit including a first PMOS transistor and a first NMOS transistor to the respective gates of which the first driving voltage and the third driving voltage are respectively input, a second push-pull output circuit including a second PMOS transistor and a second NMOS transistor to the respective gates of which the second driving voltage and the fourth driving voltage are respectively input and a common output terminal connected to the output terminal of the first push-pull output circuit and the output terminal of the second push-pull output circuit in common.
    Type: Application
    Filed: February 6, 2002
    Publication date: August 15, 2002
    Applicant: NEC CORPORATION
    Inventor: Akio Hosokawa
  • Publication number: 20010025996
    Abstract: The present invention provides a semiconductor device comprising: a load connected between outputs of power amplifiers; a mirror current generating circuit connected to the power amplifiers in an output side of the power amplifiers for generating a mirror current which is smaller than and proportional to a load current applied to the load, and the mirror current generating circuit being connected out of a current path through the load between the outputs of the power amplifiers; and a mirror current detecting circuit connected to the mirror current generating circuit for detecting the mirror current.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 4, 2001
    Applicant: NEC CORPORATION
    Inventor: Akio Hosokawa
  • Patent number: 5903422
    Abstract: An overcurrent sensing circuit for sensing an overcurrent flowing through a power MOS transistor is described. A voltage drop equal to the voltage across the drain and source of a power MOS transistor that changes due to change in a load current is generated in a sensing resistor that is connected between the source of a sensing MOS transistor having its gate and drain connected in common with those of the power MOS transistor and the source of the power MOS transistor due to current that flows through the sensing MOS transistor. This voltage is inputted to a comparator that has an added offset voltage, and the comparator judges that the power MOS transistor is in an overcurrent condition when this inputted voltage exceeds an input offset voltage value that is set inside the comparator.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: May 11, 1999
    Assignee: NEC Corporation
    Inventor: Akio Hosokawa
  • Patent number: 4696947
    Abstract: A nematocide comprises S-methyl-N,N-di-C.sub.1-2 alkyl thiolcarbamate as an active ingredient.
    Type: Grant
    Filed: February 1, 1983
    Date of Patent: September 29, 1987
    Assignee: Hodogaya Chemical Co., Ltd.
    Inventors: Yasuhisa Kurosu, Hiroshi Kawada, Haruki Kanasugi, Akio Hosokawa