Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract: To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a semiconductor element is formed. In an epitaxial layer of the peripheral region surrounding the cell region in which the semiconductor element is formed, a trench spirally surrounding the cell region and having the first and second side faces making up the corner is formed and the trench is filled with the epitaxial layer. By spirally arranging the p-type column region (n-type column region) in such a manner, a drop in a withstand voltage margin due to a hot spot can be avoided. In addition, the continuity of the p-type column region (n-type column region) is maintained. As a result, electric field concentration is alleviated step by step toward the outer periphery and the withstand voltage is therefore increased.

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: The nutritionally and/or medically significant measured value on mineral elements contained in the body of a test subject can be detected by a hair test. The signal ratio PXRF(S) of said mineral element contained in the hair of said test subject to sulfur contained therein is measured by fluorescent X-ray spectroscopy, and then is multiplied by a conversion factor F to determine the element content MXRF of the mineral element in the hair. This conversion factor F is calculated according to the formula F=M0.ICP/P0.XRF(S), wherein P0XRF(S) is a reference signal ratio of the mineral element contained in reference hair collected from a person exclusive of the test subject, and M0.ICP is a reference element content of the mineral element therein as determined by inductivity coupled plasma mass spectroscopy.

Abstract: To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a semiconductor element is formed. In an epitaxial layer of the peripheral region surrounding the cell region in which the semiconductor element is formed, a trench spirally surrounding the cell region and having the first and second side faces making up the corner is formed and the trench is filled with the epitaxial layer. By spirally arranging the p-type column region (n-type column region) in such a manner, a drop in a withstand voltage margin due to a hot spot can be avoided. In addition, the continuity of the p-type column region (n-type column region) is maintained. As a result, electric field concentration is alleviated step by step toward the outer periphery and the withstand voltage is therefore increased.

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract: Disclosed is a measurement method performed by a numerical control device measurement apparatus having a device for computing and storing the difference between a number of feedback pulses, each of which is generated whenever a movable element moves by a predetermined amount, and a number of command pulses (P.sub.s) generated by a pulse distributor, a motor being controlled in such a manner that said difference approaches zero. Specifically, the measurement method includes counting, by the storage and computing means sensor pulses (MP) generated by a sensor, reading the counted value in the storage and computing device and applying the same to the pulse distributor as a command, computing and storing, by the storage and computing device, the difference between the number of sensor pulses (MP) and the number of distributed pulses (P.sub.