Patents by Inventor Akio Inohara

Akio Inohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7005741
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: February 28, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
  • Patent number: 6933607
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: August 23, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
  • Publication number: 20030067072
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.
    Type: Application
    Filed: October 30, 2002
    Publication date: April 10, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
  • Publication number: 20030062623
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.
    Type: Application
    Filed: October 29, 2002
    Publication date: April 3, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
  • Patent number: 6525422
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: February 25, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
  • Patent number: 5372837
    Abstract: A method of manufacturing a thin film electroluminescent (EL) device in which an electron beam is directed to a pellet of a substance containing an additive agent, and the substance is evaporated and deposited on a substrate and a change per unit time of the growing deposit is monitored by a sensor, comprising the steps of (1) controlling energy of the electron beam in accordance with an output of the sensor during a first time interval for adjusting an evaporation rate of the substance to a specified rate, (2) maintaining the controlled energy of the electron beam constant during a second time interval, larger than the first time interval and alternatively repeating steps (1) and (2).
    Type: Grant
    Filed: June 22, 1993
    Date of Patent: December 13, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Shimoyama, Noriaki Nakamura, Kinichi Isaka, Akio Inohara, Hiroshi Kishishita
  • Patent number: 5325107
    Abstract: A display device, such as thin film EL display device, is formed by interposing a dielectric layer between a plurality of scanning electrodes and a plurality of data electrodes which are arranged at right angles. Modulation voltage is varied in accordance to the display data, and is applied to the data electrodes. Further, a writing voltage is applied to the scanning electrodes in sequential line order, to thereby perform gradation display. Further, the writing voltage includes a ramp voltage, which varies with time. Thus, the peak of the current flowing through the luminescent layer of the picture element, as a current contributing to the luminescence, is suppressed to a low level. contributing to the luminescence, is suppressed to a low level. Accordingly, the energization period of the current is also elongated. Thus gradation display over multiple levels is made possible and a stable display of different gradation levels is enabled.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: June 28, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ikuo Ogawa, Akio Inohara, Toshihiro Ohba, Hiroshi Kishishita, Hisashi Uede
  • Patent number: 5288515
    Abstract: There is provided a vapor deposition method for depositing a deposition material of an evaporation source on a substrate while a temperature of the substrate is uniformly kept. The method is implemented in a vapor deposition apparatus in which the evaporation source comprising the deposition material is opposed to the substrate in a vacuum chamber, a heater for heating the substrate is provided across the substrate from the evaporation source in the vacuum chamber and an equalizing plate is provided between the substrate and the heater. In addition, the equalizing plate is larger in size than the substrate and its thermal conductivity is 200 W.multidot.m.sup.-1 .multidot.K.sup.-1 or more and an infrared energy emissivity is 0.2 or more.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: February 22, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noriaki Nakamura, Hiroyuki Shimoyama, Kinichi Isaka, Akio Inohara, Hiroshi Kishishita
  • Patent number: 5137205
    Abstract: A wiring circuit substrate comprises first circuit element means one one side of the substrate connected to electrode lines of X-Y matrix electrodes, respectively, and second circuit element means in the symmetrical position of the first circuit element means on the other side of the substrate connected to the electrode lines of the X-Y matrix electrodes, respectively, wherein each of leads of the first and the second circuit element means is connected to the output and input lines of the X-Y matrix electrodes via through holes, respectively.The first circuit element comprises integrated transisitors for driving the X-Y matrix electrodes. The second circuit element comprises integrated diodes for protecting an overcurrent in the X-Y matrix electrodes.
    Type: Grant
    Filed: February 20, 1991
    Date of Patent: August 11, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akio Inohara, Yuji Ohno, Kiyoshi Sawae, Yoshiharu Kanatani, Hisashi Uede, Takeo Fujimoto
  • Patent number: 5032829
    Abstract: A thin film EL display device is described which comprises a group of parallel scanning electrodes, a group of parallel data electrodes laid so as to extend perpendicular to the group of the scanning electrodes, and an EL layer disposed between the respective groups of the scanning and data electrodes. Each of the electrodes of at least one of the groups of the scanning and data electrodes which apply a writing voltage to the EL layer is connected with a driver circuit of high voltage breakdown characteristic having only a push-pull function or a pull-up and pull-down function. This driver circuit employs thyristors as switching elements.
    Type: Grant
    Filed: September 15, 1988
    Date of Patent: July 16, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuo Shoji, Toshihiro Ohba, Akio Inohara, Hiroshi Kishishita, Hisashi Ueda
  • Patent number: 4357557
    Abstract: A thin-film electroluminescent display panel is sealed by a pair of glass substrates for protection from the environment. A protective liquid is introduced between a counter glass substrate and a substrate for supporting the electroluminescent display unit. The protective liquid comprises silicone oil or grease which assures the thin-film electroluminescent film of preservation in the electroluminescent display panel. The counter glass substrate is bonded to the support substrate through an adhesive of, for example, photo-curing resin. A capillary tube is provided within the glass substrate for injecting the liquid under vacuum conditions. The liquid has the capability of spreading into pin holes generated on dielectric layers, and is resistant to high voltage, high humidity and high temperature and is inert to layers constituting the thin-film electroluminescent display panel and has a small vapour pressure and a small coefficient of thermal expansion.
    Type: Grant
    Filed: March 14, 1980
    Date of Patent: November 2, 1982
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akio Inohara, Kiyoshi Sawae, Masashi Kawaguchi, Kinichi Isaka
  • Patent number: 4347074
    Abstract: A sealing technique is disclosed by which the firing voltage of atmospheric discharge is increased by a pressurizing procedure such that the internal pressure of a sealing chamber is held at room temperature above half (0.5) of the atmospheric pressure even after the completion of sealing. Preferably, the pressurizing procedure is accomplished by a partial modification in the existing sealing facilities (for example, belt furnaces and low temperature furnaces). In another aspect of the invention, the method for sealing a semiconductor device minimizes water in the chamber after sealing by suppressing water expelled from glass frit during sealing or allowing the glass frit to absorb the water expelled therefrom. In other words, sealing is performed first under nitrogen gas atmosphere and then under oxygen gas atmosphere.
    Type: Grant
    Filed: November 17, 1980
    Date of Patent: August 31, 1982
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akio Inohara, Kiyoshi Sawae, Hisao Kawaguchi, Takeo Fujimoto
  • Patent number: 4159921
    Abstract: A connection apparatus mainly comprises a gas-tight container one surface of which is made of a film, a gas supply source for filling the container with a gas at a predetermined pressure, and a heat source. Two substrates, at least one of which is flexible, are tightly supported on the film surface of the container in such a manner that electrodes or terminals formed on the both substrates confront with each other. The gas pressure in the container is increased to the predetermined value, thereby to tightly contact the electrodes formed on the both substrates with each other. Thereafter, the heat source is enabled to melt the electrodes and to electrically connect the two substrates with each other.
    Type: Grant
    Filed: January 16, 1978
    Date of Patent: July 3, 1979
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akio Inohara, Koji Takahashi, Ryoji Inoue
  • Patent number: D322603
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: December 24, 1991
    Assignee: Sharp Corporation
    Inventors: Hisashi Uede, Hiroshi Kishishita, Akio Inohara, Kyouichi Yamamoto, Ikuo Ogawa