Patents by Inventor Akio Inohara
Akio Inohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7005741Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.Type: GrantFiled: October 30, 2002Date of Patent: February 28, 2006Assignee: Sharp Kabushiki KaishaInventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
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Patent number: 6933607Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.Type: GrantFiled: October 29, 2002Date of Patent: August 23, 2005Assignee: Sharp Kabushiki KaishaInventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
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Publication number: 20030067072Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.Type: ApplicationFiled: October 30, 2002Publication date: April 10, 2003Applicant: Sharp Kabushiki KaishaInventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
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Publication number: 20030062623Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.Type: ApplicationFiled: October 29, 2002Publication date: April 3, 2003Applicant: Sharp Kabushiki KaishaInventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
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Patent number: 6525422Abstract: A semiconductor device includes a semiconductor substrate, a plurality of electrode pads aligned on the semiconductor substrate, and a plurality of bump electrodes placed on each electrode pad, wherein the plurality of bump electrodes on the electrode pad are aligned in a direction orthogonal to a direction where the electrode pads are aligned. A manufacturing method of the semiconductor device includes the steps of patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads and forming a bump electrode in a perpendicular straight wall shape to be thinner than the photoresist by plating the bump electrode forming use metal to the electrode pad.Type: GrantFiled: December 11, 1997Date of Patent: February 25, 2003Assignee: Sharp Kabushiki KaishaInventors: Atsushi Ono, Yasunori Chikawa, Makoto Kanda, Norimitsu Nie, Satoru Tone, Motoji Shiota, Akio Inohara, Hirokazu Yoshida
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Patent number: 5372837Abstract: A method of manufacturing a thin film electroluminescent (EL) device in which an electron beam is directed to a pellet of a substance containing an additive agent, and the substance is evaporated and deposited on a substrate and a change per unit time of the growing deposit is monitored by a sensor, comprising the steps of (1) controlling energy of the electron beam in accordance with an output of the sensor during a first time interval for adjusting an evaporation rate of the substance to a specified rate, (2) maintaining the controlled energy of the electron beam constant during a second time interval, larger than the first time interval and alternatively repeating steps (1) and (2).Type: GrantFiled: June 22, 1993Date of Patent: December 13, 1994Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Shimoyama, Noriaki Nakamura, Kinichi Isaka, Akio Inohara, Hiroshi Kishishita
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Patent number: 5325107Abstract: A display device, such as thin film EL display device, is formed by interposing a dielectric layer between a plurality of scanning electrodes and a plurality of data electrodes which are arranged at right angles. Modulation voltage is varied in accordance to the display data, and is applied to the data electrodes. Further, a writing voltage is applied to the scanning electrodes in sequential line order, to thereby perform gradation display. Further, the writing voltage includes a ramp voltage, which varies with time. Thus, the peak of the current flowing through the luminescent layer of the picture element, as a current contributing to the luminescence, is suppressed to a low level. contributing to the luminescence, is suppressed to a low level. Accordingly, the energization period of the current is also elongated. Thus gradation display over multiple levels is made possible and a stable display of different gradation levels is enabled.Type: GrantFiled: May 28, 1993Date of Patent: June 28, 1994Assignee: Sharp Kabushiki KaishaInventors: Ikuo Ogawa, Akio Inohara, Toshihiro Ohba, Hiroshi Kishishita, Hisashi Uede
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Patent number: 5288515Abstract: There is provided a vapor deposition method for depositing a deposition material of an evaporation source on a substrate while a temperature of the substrate is uniformly kept. The method is implemented in a vapor deposition apparatus in which the evaporation source comprising the deposition material is opposed to the substrate in a vacuum chamber, a heater for heating the substrate is provided across the substrate from the evaporation source in the vacuum chamber and an equalizing plate is provided between the substrate and the heater. In addition, the equalizing plate is larger in size than the substrate and its thermal conductivity is 200 W.multidot.m.sup.-1 .multidot.K.sup.-1 or more and an infrared energy emissivity is 0.2 or more.Type: GrantFiled: February 8, 1993Date of Patent: February 22, 1994Assignee: Sharp Kabushiki KaishaInventors: Noriaki Nakamura, Hiroyuki Shimoyama, Kinichi Isaka, Akio Inohara, Hiroshi Kishishita
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Patent number: 5137205Abstract: A wiring circuit substrate comprises first circuit element means one one side of the substrate connected to electrode lines of X-Y matrix electrodes, respectively, and second circuit element means in the symmetrical position of the first circuit element means on the other side of the substrate connected to the electrode lines of the X-Y matrix electrodes, respectively, wherein each of leads of the first and the second circuit element means is connected to the output and input lines of the X-Y matrix electrodes via through holes, respectively.The first circuit element comprises integrated transisitors for driving the X-Y matrix electrodes. The second circuit element comprises integrated diodes for protecting an overcurrent in the X-Y matrix electrodes.Type: GrantFiled: February 20, 1991Date of Patent: August 11, 1992Assignee: Sharp Kabushiki KaishaInventors: Akio Inohara, Yuji Ohno, Kiyoshi Sawae, Yoshiharu Kanatani, Hisashi Uede, Takeo Fujimoto
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Patent number: 5032829Abstract: A thin film EL display device is described which comprises a group of parallel scanning electrodes, a group of parallel data electrodes laid so as to extend perpendicular to the group of the scanning electrodes, and an EL layer disposed between the respective groups of the scanning and data electrodes. Each of the electrodes of at least one of the groups of the scanning and data electrodes which apply a writing voltage to the EL layer is connected with a driver circuit of high voltage breakdown characteristic having only a push-pull function or a pull-up and pull-down function. This driver circuit employs thyristors as switching elements.Type: GrantFiled: September 15, 1988Date of Patent: July 16, 1991Assignee: Sharp Kabushiki KaishaInventors: Kazuo Shoji, Toshihiro Ohba, Akio Inohara, Hiroshi Kishishita, Hisashi Ueda
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Patent number: 4357557Abstract: A thin-film electroluminescent display panel is sealed by a pair of glass substrates for protection from the environment. A protective liquid is introduced between a counter glass substrate and a substrate for supporting the electroluminescent display unit. The protective liquid comprises silicone oil or grease which assures the thin-film electroluminescent film of preservation in the electroluminescent display panel. The counter glass substrate is bonded to the support substrate through an adhesive of, for example, photo-curing resin. A capillary tube is provided within the glass substrate for injecting the liquid under vacuum conditions. The liquid has the capability of spreading into pin holes generated on dielectric layers, and is resistant to high voltage, high humidity and high temperature and is inert to layers constituting the thin-film electroluminescent display panel and has a small vapour pressure and a small coefficient of thermal expansion.Type: GrantFiled: March 14, 1980Date of Patent: November 2, 1982Assignee: Sharp Kabushiki KaishaInventors: Akio Inohara, Kiyoshi Sawae, Masashi Kawaguchi, Kinichi Isaka
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Patent number: 4347074Abstract: A sealing technique is disclosed by which the firing voltage of atmospheric discharge is increased by a pressurizing procedure such that the internal pressure of a sealing chamber is held at room temperature above half (0.5) of the atmospheric pressure even after the completion of sealing. Preferably, the pressurizing procedure is accomplished by a partial modification in the existing sealing facilities (for example, belt furnaces and low temperature furnaces). In another aspect of the invention, the method for sealing a semiconductor device minimizes water in the chamber after sealing by suppressing water expelled from glass frit during sealing or allowing the glass frit to absorb the water expelled therefrom. In other words, sealing is performed first under nitrogen gas atmosphere and then under oxygen gas atmosphere.Type: GrantFiled: November 17, 1980Date of Patent: August 31, 1982Assignee: Sharp Kabushiki KaishaInventors: Akio Inohara, Kiyoshi Sawae, Hisao Kawaguchi, Takeo Fujimoto
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Patent number: 4159921Abstract: A connection apparatus mainly comprises a gas-tight container one surface of which is made of a film, a gas supply source for filling the container with a gas at a predetermined pressure, and a heat source. Two substrates, at least one of which is flexible, are tightly supported on the film surface of the container in such a manner that electrodes or terminals formed on the both substrates confront with each other. The gas pressure in the container is increased to the predetermined value, thereby to tightly contact the electrodes formed on the both substrates with each other. Thereafter, the heat source is enabled to melt the electrodes and to electrically connect the two substrates with each other.Type: GrantFiled: January 16, 1978Date of Patent: July 3, 1979Assignee: Sharp Kabushiki KaishaInventors: Akio Inohara, Koji Takahashi, Ryoji Inoue
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Patent number: D322603Type: GrantFiled: February 28, 1989Date of Patent: December 24, 1991Assignee: Sharp CorporationInventors: Hisashi Uede, Hiroshi Kishishita, Akio Inohara, Kyouichi Yamamoto, Ikuo Ogawa