Patents by Inventor Akio Katsushima

Akio Katsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8981825
    Abstract: A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Akio Katsushima
  • Publication number: 20140320185
    Abstract: A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator.
    Type: Application
    Filed: July 14, 2014
    Publication date: October 30, 2014
    Inventor: Akio KATSUSHIMA
  • Patent number: 8810292
    Abstract: A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Akio Katsushima
  • Patent number: 7580443
    Abstract: In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: August 25, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Uemura, Takashi Nakamura, Akio Katsushima, Makoto Funatsu
  • Publication number: 20060176933
    Abstract: In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.
    Type: Application
    Filed: January 13, 2006
    Publication date: August 10, 2006
    Inventors: Yasuhiro Uemura, Takashi Nakamura, Akio Katsushima, Makoto Funatsu