Abstract: To provide a digital integrating circuit which can increase speed by preventing the influence of a delay in carry propagation and can obtain an accumulated value for each section at a higher sampling frequency, the carry holding type adder 4 and the carry propagation type adder 7 are combined and a plurality of holding registers 51 to 53 and a plurality of result storage registers 81 to 83 are provided to store the results of additions. A single holding register is effective for each section and these holding registers 51 to 53 are structured as shift registers after completion of accumulation for all the sections so that accumulated data stored in the holding registers are sequentially input into the carry propagation type adder to output final accumulated data for each section.

Abstract: A circuit for reducing the number of times a character read-only memory (ROM) in a video display must be accessed in order to display outlined characters. For each pixel on a scan line in a character to be displayed the circuit outputs information on the current scan line and the scan lines above and below the current scan line. The pixels above and below the current pixel on the current scan line are summed and output as a single value. Thus, the number of accesses to the character ROM is reduced from three to two.

Abstract: A screen display device which displays characters and patterns on a TV screen or other screen having a separate blanking signal output controlled by set data for each character in the display memory. Different displays can be shown on several different screens by controlling a color signal which combines the set data for each character and the set data for each screen.

Abstract: The voltage of a CPU operation power source is stepped down by a regulator to a voltage for causing oscillation of an oscillator. The output voltage of the oscillator is stepped up by a level shifter.

Abstract: A high voltage switch circuit, wherein the source of a first MOS transistor is connected to the gate of a second MOS transistor, the source of the second MOS transistor is connected to the gate of the first MOS transistor, the drain of a third MOS transistor and the gate of a fourth MOS transistor, the drains of the first and fourth MOS transistors are connected to a high voltage input terminal, the sources of the third and fourth MOS transistors are connected to an output terminal, a voltage for turning the transistor ON is applied to the gate of the third MOS transistor, one electrodes of two independent capacitors are connected to the gates of the first and second MOS transistors, and a clock is applied through transmission gates to the other electrode of the two capacitors.