Patents by Inventor Akio Kuito

Akio Kuito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Plastic encapsulated semiconductor device and method of manufacturing the same
    Patent number: 6130115
    Abstract: A plastic encapsulated semiconductor device comprises a die pad, die pad support pins suspending the die pad, a semiconductor chip mounted on the die pad, thin metal wires for connecting the electrode of the semiconductor chip to leads, and a sealing resin sealing the foregoing components, while the respective bottom faces of the leads forming terminal portions are exposed. An upset process is performed with respect to the die pad support pins of a lead frame to form stepped portions such that the die pad is positioned higher in level than the leads. Since the lower portion of the sealing resin also underlies the die pad, enhanced adhesion is achieved between the die pad and the sealing rein, resulting in higher reliability. With the die pad positioned higher in level than the leads, there is no possibility of interference between the leads and the semiconductor chip even when the size of the semiconductor chip is freely changed.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: October 10, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Ichiro Okumura, Masanori Minamio, Akio Kuito, Takeshi Morikawa, Toshiyuki Fukuda, Fumito Itoh
  • Plastic encapsulated semiconductor device and method of manufacturing the same
    Patent number: 5942794
    Abstract: A plastic encapsulated semiconductor device comprises a die pad, die pad support pins suspending the die pad, a semiconductor chip mounted on the die pad, thin metal wires for connecting the electrode of the semiconductor chip to leads, and a sealing resin sealing the foregoing components, while the respective bottom faces of the leads forming terminal portions are exposed. An upset process is performed with respect to the die pad support pins of a lead frame to form stepped portions such that the die pad is positioned higher in level than the leads. Since the lower portion of the sealing resin also underlies the die pad, enhanced adhesion is achieved between the die pad and the sealing rein, resulting in higher reliability. With the die pad positioned higher in level than the leads, there is no possibility of interference between the leads and the semiconductor chip even when the size of the semiconductor chip is freely changed.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: August 24, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Ichiro Okumura, Masanori Minamio, Akio Kuito, Takeshi Morikawa, Toshiyuki Fukuda, Fumito Itoh