Patents by Inventor Akio Machida

Akio Machida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6645837
    Abstract: A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: November 11, 2003
    Assignee: Sony Corporation
    Inventors: Dharam Pal Gosain, Kazumasa Nomoto, Akio Machida, Miyako Nakagoe, Setsuo Usui
  • Publication number: 20030173601
    Abstract: A functional device free from cracking and having excellent functional characteristics, and a method of manufacturing the same are disclosed. A low-temperature softening layer (12) and a heat-resistant layer (13) are formed in this order on a substrate (11) made of an organic material such as polyethylene terephthalate, and a functional layer (14) made of polysilicon is formed thereon. The functional layer (14) is formed by crystallizing an amorphous silicon layer, which is a precursor layer, with laser beam irradiation. When a laser beam is applied, heat is transmitted to the substrate (11) and the substrate (11) tends to expand. However, a stress caused by a difference in a thermal expansion coefficient between the substrate (11) and the functional layer (14) is absorbed by the low-temperature softening layer (12), so that no cracks and peeling occurs in the functional layer (14). The low-temperature softening layer (12) is preferably made of a polymeric material containing an acrylic resin.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 18, 2003
    Inventors: Akio Machida, Dharam Pal Gosain, Setsuo Usui
  • Patent number: 6610548
    Abstract: An epitaxial rare earth oxide (001)/silicon (001) structure is realized by epitaxially growing a rare earth oxide such as cerium dioxide in the (001) orientation on a (001)-oriented silicon substrate. For this purpose, the surface of the (001)-oriented Si substrate is processed into a dimer structure by 2×1, 1×2 surface reconstruction, and a rare earth oxide of a cubic system or a tetragonal system, such as CeO2 film, is epitaxially grown in the (001) orientation on the Si substrate by molecular beam epitaxy, for example. During this growth, a source material containing at least one kind of rare earth element is supplied after the supply of an oxidic gas is supplied onto the surface of the Si substrate. If necessary, annealing is conducted in vacuum after the growth.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: August 26, 2003
    Assignee: Sony Corporation
    Inventors: Takaaki Ami, Yuichi Ishida, Naomi Nagasawa, Masayuki Suzuki, Akio Machida
  • Publication number: 20030136331
    Abstract: An epitaxial rare earth oxide (001)/silicon (001) structure is realized by epitaxially growing a rare earth oxide such as cerium dioxide in the (001) orientation on a (001)-oriented silicon substrate. For this purpose, the surface of the (001)-oriented Si substrate is processed into a dimer structure by 2×1, 1×2 surface reconstruction, and a rare earth oxide of a cubic system or a tetragonal system, such as CeO2 film, is epitaxially grown in the (001) orientation on the Si substrate by molecular beam epitaxy, for example. During this growth, a source material containing at least one kind of rare earth element is supplied after the supply of an oxidic gas is supplied onto the surface of the Si substrate. If necessary, annealing is conducted in vacuum after the growth.
    Type: Application
    Filed: January 30, 2003
    Publication date: July 24, 2003
    Inventors: Takaaki Ami, Yuichi Ishida, Naomi Nagasawa, Masayuki Suzuki, Akio Machida
  • Publication number: 20030136440
    Abstract: An optical energy conversion apparatus 10 includes a first impurity doped semiconductor layer 5, formed on a substrate, and which is of a semiconductor material admixed with a first impurity, an optically active layer 6, formed on the first impurity doped semiconductor layer 5, and which is of a hydrogen-containing amorphous semiconductor material, and a second impurity doped semiconductor layer 7, admixed with a second impurity and formed on the optically active semiconductor layer 6. The second impurity doped semiconductor layer is of a polycrystallized semiconductor material lower in hydrogen concentration than the material of the optically active semiconductor layer 6. The average crystal grain size in the depth-wise direction in an interfacing structure between the optically active semiconductor layer 6 and the second impurity doped semiconductor layer 7 is decreased stepwise in a direction proceeding from the surface of the second impurity doped semiconductor layer towards the substrate 1.
    Type: Application
    Filed: December 19, 2002
    Publication date: July 24, 2003
    Inventors: Akio Machida, Setsuo Usui, Kazumasa Nomoto
  • Patent number: 6570223
    Abstract: A functional device and method of manufacturing the same are disclosed. A low-temperature softening layer and a heat-resistant layer are formed in this order on a substrate made of organic material such as polyethylene terephthalate, and a functional layer made of polysilicon is formed thereon. The functional layer is formed by crystallizing an amorphous silicon layer (precursor layer), with laser beam irradiation. When a laser beam is applied, heat causes the substrate to expand. However, stress caused by a difference in a thermal expansion coefficient between the substrate and the functional layer is absorbed by the low-temperature softening layer, so that no cracks and peeling occurs in the functional layer. The low-temperature softening layer is preferably made of a polymeric material containing acrylic resin. By properly interposing a metal layer and a heat-resistant layer between the substrate and the functional layer, a laser beam of higher intensity can be irradiated.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: May 27, 2003
    Assignee: Sony Corporation
    Inventors: Akio Machida, Dharam Pal Gosain, Setsuo Usui
  • Publication number: 20030077886
    Abstract: A lower concentration impurity diffusion region can be formed under excellent control, even when a low heat-resistant substrate is used. At the time of doping a semiconductor layer, a mask such as sidewalls (24) where an energy beam passes through, is formed on a part of a surface of a semiconductor layer (21), dopant ions (25) are adsorbed on the surface of the semiconductor layer (21) except a region in which the mask is formed, and an energy beam EBL is irradiated onto the semiconductor layer (21) having the formed mask to introduce the dopant ions into the semiconductor layer (21). In the lower part of the mask such sidewalls (24), diffusion in transverse direction occurs and lower concentration impurity diffusion regions can be formed in excellent reproducibility under excellent control.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 24, 2003
    Inventors: Akio Machida, Setsuo Usui, Dharam Pal Gosain
  • Publication number: 20020130337
    Abstract: It is intended to provide a ferroelectric that exhibits superior ferroelectricity. A ferroelectric provided is an oxide having a layered crystal structure that is composed of Bi, a first element Me, a second element R, and O. The first element Me is at least one element selected from the group consisting of Na, K, Ca, Ba, Sr, Pb, and Bi. The second element R is at least one element selected from the group consisting of Fe, Ti, Nb, Ta, and W. Ninety-eight percent or more of the entire body of the ferroelectric exhibits ferroelectricity. After an oxide having a layered crystal structure has been grown by a vapor-phase method (crystal growth step), electrodes are attached to the oxide having a layered crystal structure and a voltage is applied thereto (voltage application step).
    Type: Application
    Filed: October 29, 1999
    Publication date: September 19, 2002
    Inventors: AKIO MACHIDA, NAOMI NAGASAWA, TAKAAKI AMI, MASAYUKI SUZUKI
  • Publication number: 20020119659
    Abstract: An epitaxial rare earth oxide (110)/silicon (001) structure is realized by epitaxially growing a rare earth oxide such as cerium dioxide in the (110) orientation on a (001)-oriented silicon substrate at a growth temperature lower than conventional ones. For this purpose, the surface of the (001)-oriented Si substrate is processed into a dimer structure by 2×1, 1×2 surface reconstruction, and a rare earth oxide of a cubic system or a tetragonal system, such as CeO2 film, is epitaxially grown in the (110) orientation on the Si substrate in an atmosphere containing an oxidic gas by using a source material made up of at least one kind of rare earth element. During this growth, a source material containing at least one kind of rare earth element is supplied after the supply of an oxidic gas is supplied onto the surface of the Si substrate.
    Type: Application
    Filed: April 19, 2002
    Publication date: August 29, 2002
    Inventors: Takaaki Ami, Yuichi Ishida, Naomi Nagasawa, Masayuki Suzuki, Akio Machida
  • Publication number: 20020016027
    Abstract: A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.
    Type: Application
    Filed: May 31, 2001
    Publication date: February 7, 2002
    Inventors: Dharam Pal Gosain, Kazumasa Nomoto, Akio Machida, Miyako Nakagoe, Setsuo Usui
  • Patent number: 6207082
    Abstract: A layer-structured oxide exhibiting a paraelectric characteristic and a layer-structured oxide having a preferable remanent polarization, and a process of producing the same. A layer-structured oxide containing Bi, a first component Me, a second component R, and O is produced by heating raw materials at a high temperature of about 1400° C. for several ten minutes by a self-flux method using Bi2O3 as a flux. The first component Me is composed of at least one kind selected from a group consisting of Sr, Pb, Ba, and Ca, and the second component R is composed of at least one kind selected from a group consisting of Nb and Ta. The composition formula of the oxide is expressed by Bi2−aMe1+bR2O9+c where a, b, and c are values in ranges of 0<a<2, 0<b≦0.4, and −0.3≦c≦1.4. The layer-structured oxide exhibits a paraelectric characteristic or a ferroelectric characteristic at a composition in a specific range out of the stoichiometric composition.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: March 27, 2001
    Assignee: Sony Corporation
    Inventors: Masayuki Suzuki, Naomi Nagasawa, Akio Machida, Takaaki Ami
  • Patent number: 6174463
    Abstract: A layer crystal structure oxide, and memory element comprising same, comprising bismuth (Bi), a first element, a second element and oxygen (O), wherein the first element is at least one selected from the group consisting of sodium (Na), potassium (K), calcium (Ca), barium (Ba), strontium (Sr), lead (Pb), and bismuth (Bi), the second element is at least one selected from the group consisting of iron (Fe), titanium (Ti), niobium (Nb), tantalum (Ta), and tungsten (W), and the composition ratio of the bismuth with respect to the second element is larger than the stoichiometric composition ratio, wherein, the composition ratio of the bismuth with respect to the first element is in the range of (2±0.17)/(m−1) including the stoichiometric composition ratio 2/(m−1), where m is an integer from, and including, 2 to 5.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: January 16, 2001
    Assignee: Sony Corporation
    Inventors: Akio Machida, Naomi Nagasawa, Takaaki Ami, Masayuki Suzuki
  • Patent number: 6171871
    Abstract: It is intended to provide a ferroelectric that exhibits superior ferroelectricity. A ferroelectric provided is an oxide having a layered crystal structure that is composed of Bi, a first element Me, a second element R, and O. The first element Me is at least one element selected from the group consisting of Na, K, Ca, Ba, Sr, Pb, and Bi. The second element R is at least one element selected from the group consisting of Fe, Ti, Nb, Ta, and W. Ninety-eight percent or more of the entire body of the ferroelectric exhibits ferroelectricity. After an oxide having a layered crystal structure has been grown by a vapor-phase method (crystal growth step), electrodes are attached to the oxide having a layered crystal structure and a voltage is applied thereto (voltage application step).
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: January 9, 2001
    Assignee: Sony Corporation
    Inventors: Akio Machida, Naomi Nagasawa, Takaaki Ami, Masayuki Suzuki
  • Patent number: 6143679
    Abstract: Provided are a layered crystal structure oxide showing ferroelectricity or paraelectricity and a process for easily producing the same. A raw material containing Bi.sub.2 O.sub.3 as a flux is heated up to 1330.degree. C. or higher and 1450.degree. C. or lower at a suitable temperature-elevating rate (heating step); the raw material is maintained at this heating temperature for prescribed time (constant temperature step); and then, it is slowly cooled down to 800.degree. C. or higher and 1300.degree. C. or lower at a rate of 1.degree. C./hour or more and 20.degree. C./hour or less (slow cooling step). This makes it possible to evaporate the flux and take out directly Bi.sub.2 SrTa.sub.2 O.sub.9. In this Bi.sub.2 SrTa.sub.2 O.sub.9, Bi is partially substituted with Sr, and oxygen is selectively deficient or disordered. Or, Bi and O in the fluorite layer are relatively displaced each other in the polarization direction.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: November 7, 2000
    Assignee: Sony Corporation
    Inventors: Naomi Nagasawa, Akio Machida, Takaaki Ami, Masayuki Suzuki
  • Patent number: 6106616
    Abstract: A production method of a crystal structure oxide that includes the steps of evaporating the material by heating the material to generate a gas phase and precipitating crystals from the gas phase at a precipitating part so as to produce a layer crystal structure oxide. The precipitating part is provided away from the material in a range of greater than or equal to about 10 mm to about 30 mm.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: August 22, 2000
    Assignee: Sony Corporation
    Inventors: Akio Machida, Naomi Nagasawa, Takaaki Ami, Masayuki Suzuki
  • Patent number: 5904766
    Abstract: Provided is a process for preparing a bismuth compound at a heat treatment temperature lower than conventional. A bismuth compound is prepared by the steps of heating under vacuum to form a reduced phase and heating under oxidizing environment of normal or lower pressure.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: May 18, 1999
    Assignee: Sony Corporation
    Inventors: Takaaki Ami, Katsuyuki Hironaka, Koji Watanabe, Akio Machida
  • Patent number: 5777977
    Abstract: A recording and reproducing apparatus has a recording and/or reading head having a tip for recording and/or reproducing information on and/or from a recording medium. Information is recorded and/or erased by way of a polarization reversal or transport of electric charges in a predetermined area of the recording medium in response to application of a pulse voltage from the head. The information recorded in the predetermined area is detected as a change in the electric charges or an electrostatic capacitance or a surface potential or their differential in the predetermined area for reproducing the information.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: July 7, 1998
    Assignee: Sony Corporation
    Inventors: Ichiro Fujiwara, Akio Machida, Shigeru Kojima