Abstract: Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels.

Abstract: A jump judgment circuit judges whether an instruction read bus cycle of a CPU to be emulated is to be executed in a sequential order of addresses of a memory. A control circuit operates in accordance with the judgment result. Specifically, if an instruction is in the sequential order of addresses of a memory relative to the immediately preceding instruction, instruction codes previously read from the memory and converted are read from a queue and supplied to the CPU. If an instruction is not in the sequential order of addresses, which would correspond to a jump to a noncontiguous address of a memory, that instruction is read from the memory at the designated address, converted into instruction codes, and supplied to CPU.

Abstract: An illegal copy prevention apparatus including a plurality of illegal copy discriminators (e.g. instructions to set flags), an event generator (e.g. detections of "0" sec in real time) corresponding to the illegal copy discriminators, and an abnormal operation generator for generating an abnormal operation when any one of the illegal discriminator and the corresponding event generator generates an event. Since the probability at which all the abnormal operations are generated by all the abnormal operation generators is low, it is extremely difficult for a violator to notice the presence of all the copy protections and further remove all the copy protections completely, thus realizing an effective illegal copy prevention apparatus for computer software and circuit configuration of IC devices.

Abstract: When a data processing instruction is given to a microprocessor, and the code of a data register subject to designation is held in an instruction register, a first logic level is outputted from the instruction code decoder, but when the register subject to designation is the instruction queuing register in which a subsequent instruction code is to be held, a second logic level is outputted from the instruction code decoder. By the operation of logic switching means, when the first logic level is being outputted, the register select code decoder can select the data register designated, while when the second logic level is being outputted, the register select code decoder can select the instruction queuing register designated. Accordingly, this eliminates the necessity of carrying out the designation of a data register or queuing register in the microprogram, thus making it possible to reduce the size of the microprogram used.

Abstract: A microprogram processor to execute high speed processing of macro instructions using microcodes is provided. This microprogram processor comprises a microcode decoder for decoding a microcode generated from a microprogram ROM in response to a macro instruction, and a jump judgement decoder responsive to a jump condition signal externally delivered and a result decoded by the microcode decoder, to generate a microjump signal when a jump condition holds. The microprogram processor further comprises a circuit for generating a next instruction start signal for immediately shifting to a next instruction on the basis of a decoded signal signifying the start of a next macro instruction when no request for a jump is outputted from the microcode decoder. Such a next instruction start signal generator circuit may be realized by a simple logic circuit. In addition, the jump judgement decoder further responds to data of a portion (e.g.

Abstract: A microprogram control device comprises a machine instruction decoder (11) for sequentially decoding machine instructions fetched from an external computer memory and providing a microcode start address for each decoded instruction, a counter (12) connected to the decoder for generating a required number of microcode addresses, a microcode storage unit (13) comprising an address decoding area (13a) in which microcodes are designated by microcode address and a microcode memory area (13b) in which the microcodes associated with the machine instructions are stored, and a microcode register (14) for controlling the operation of circuits (25) to be controlled and for providing a control signal output (Sc) to the counter. A "don't care" function is associated with certain bit positions of microcode addresses of microsteps common to sequential machine instructions. In this manner memory chip area may be reduced without any decrease in microcomputer operating speed.

Abstract: In the copy prevention apparatus and its method, it is discriminated whether an object is legally copied or not; a constant event is generated at or below a predetermined probability; and an abnormal operation is executed only if the two conditions of the object having been determined as an illegal copy, and the event having been generated, are satisfied. Therefore, even if the object is determined as an illegal copy, the abnormal operation is not always executed, but executed at or below a predetermined probability. Although the occurrence of the abnormal operation can be indicated to the user immediately, it is also preferable to keep the abnormal operation occurrence secret for a time and inform the user of the occurrence an appropriate time later.

Abstract: A microprogram processor to execute high speed memory access when an operand indicates a memory is provided. This microprogram processor comprises an instruction register for holding a unit length of an instruction code, an instruction decoder for decoding an instruction code in the register, thus generating a signal dependent upon the fact that the operand indicates a register or a memory, a microcode decoder for decoding a microcode generated from a ROM depending upon the instruction code, thus generating a noncondition memory access signal and a next instruction start condition signal, and a next instruction start condition judgement decoder connected to receive both an output from the instruction code decoder and the next instruction start condition signal to judge whether or not the next instruction start is correct. The microcode decoder further generates a conditional memory access signal when the operand indicates a memory. Thus, a memory access signal generator circuit, e.g.

Abstract: A divisional operation is performed by the invention, using three registers. The higher order digits or figures of dividend are given to the first register and the lower order digits or figures thereof are given to the second register. In addition, a divisor is given to the third register. Subtraction is performed between the content of the first register and the content of the third register. On the basis of the sign of the result, the quotient is determined. Every time subtraction is performed, a shift operation is conducted in the first and second registers. The quotient is stored in the second register from the least significant bit thereof. In such a shift operation, data of 1 bit is transferred from the most significant bit of the second register to the least significant bit of the first register. Where the data of 1 bit thus transferred represents "1" when the operation is completed, it is detected that division is in an overflow state.

Abstract: A microprocessor having variable data width comprising a bus cycle changeover circuit between a command execution unit and each of an address output logic, a data input/output logic, and a bus controller. The bus cycle changeover circuit receives an address, data, a memory access instruction and a data width instruction from the command execution unit and modifies timings of them according to an externally supplied data width selection signal and transmits modified address, data, memory access instruction and data width instruction signals to the address output logic, the data input/output logic and the bus controller. The bus cycle changeover circuit comprises a cycle control circuit which outputs a signal expressing a latter half access cycle and an upper/lower selection circuit which selects upper/lower parts of the data bus according to an output signal of the cycle control circuit.

Abstract: A hermetic sealing cover assembly for a semiconductor device, etc. has a seal ring and a metallic cover joined thereto. The seal ring has a thin layer of gold, silver, platinum or palladium. The cover has a film of a material of high solderability, such as gold or nickel, formed at least on the peripheral edge of its surface facing the seal ring. The ring is joined in its entirety to the peripheral edge of the cover so that the layer on the ring may be bonded to the film on the cover. A method of producing such a sealing cover assembly is also disclosed.

Abstract: The invention concerns a portable electromagnetic pneumatic power drill. It may be used to make rivet or bolt holes in structural steel girders in guilding and bridge construction. The base of the drill stand is secured to the steel workpiece by electromagnetism. Exhaust air from the drill head cools the electromagnetic base as well as the bit and workpiece. Drill chips are diverted by the exhaust stream and deflected from the rack slide mechanism by a shield. This allows the slide to approach the base and workpiece very closely to improve steadiness and accuracy of drilling.

Abstract: A copper alloy which is high in strength and electroconductivity is manufactured by casting, without chill casting, a copper alloy mass substantially consisting of copper and containing 0.2 to 1.5% by weight of chromium and 0.01 to 0.5% by weight of tin, hot working the cast copper alloy mass, then cooling, not slowly, the hot worked alloy mass without being subjected to any solid solution treatment, further cold working the cooled alloy mass, and thereafter subjecting the cold worked alloy mass to an aging treatment.