Abstract: A display device comprises scan lines on a insulating substrate, signal lines intersecting with the scan lines with an insulating film interposed therebetween, a display area comprising pixel electrodes connected to the signal lines, a scan line driver circuit connected to the scan lines, a signal line driver circuit connected to the signal lines. The scan line driver circuit and the signal line driver circuit are mounted directly on the insulating substrate outside of the display area and close to one side of the display area. Lines connecting the scan line driver circuit and the signal line driver circuit are formed in an area in which the scan line driver circuit and the signal line driver circuit are mounted.

Abstract: A display device having a substrate provided with a display region includes a lower layer film formed on the substrate, a transparent conductive thin film formed on the lower layer film and electrically connected thereto, and a protective film formed on the transparent conductive film in a region other than the display region to prevent malformation of the transparent conductive thin film and the lower layer film.

Abstract: An array substrate according to the invention includes an external terminal formed in the vicinity of an end portion of an insulating substrate so as to supply electric potential from the exterior to a driving circuit, a signal line monitoring terminal formed in parallel with the external terminal, a signal line branch terminal formed in such a way as to be connected to a signal line or to a signal line terminal, and an internal terminal associated with the signal line monitoring terminal, which is connected to the signal line monitoring terminal and connectable to a signal line branch terminal by an electrically conductive material and a bump of the driving circuit.

Abstract: A display device includes a scanning line (1) formed on an insulating substrate; a storage capacitance line (3) formed in parallel to the scanning line; an image signal line (2) formed across the scanning line (1) and the storage capacitance line (3) through an insulating layer; and a pixel electrode (6) being surrounded with the scanning line (1), the storage capacitance line (3) and the image signal line (2); wherein at least one overlapped area (11) of the storage capacitance line (3) and the image signal line (2) is defined in the area other than the crossing region of the storage capacitance line (3) and the image signal line (2) within one pixel area; whereby, breakage of the image signal line is mended without increasing the production steps, and production yield is improved.

Abstract: A display device comprises scan lines on a insulating substrate, signal lines intersecting with the scan lines with an insulating film interposed therebetween, a display area comprising pixel electrodes connected to the signal lines, a scan line driver circuit connected to the scan lines, a signal line driver circuit connected to the signal lines. The scan line driver circuit and the signal line driver circuit are mounted directly on the insulating substrate outside of the display area and close to one side of the display area. Lines connecting the scan line driver circuit and the signal line driver circuit are formed in an area in which the scan line driver circuit and the signal line driver circuit are mounted.

Abstract: The present invention is directed to a display device including a scanning line (1) formed on an insulating substrate; a storage capacitance line (3) formed in parallel to said scanning line; an image signal line (2) formed across said scanning line (1) and said storage capacitance line (3) through an insulating layer; and a pixel electrode (6) being surrounded with said scanning line (1), said storage capacitance line (3) and said image signal line (2); wherein at least one overlapped area (11) of said storage capacitance line (3) and said image signal line (2) is defined in the area other than the crossing region of the storage capacitance line (3) and the image signal line (2) within one pixel area; whereby, breakage of the image signal line is mended without increasing the production step, and production yield is improved.

Abstract: In the display area of the TFT array substrate, a pixel electrode, a switching element connected to the pixel electrode, a gate line connected to the switching element and a source line connected to the switching element are formed. In the terminal forming area of the TFT substrate, a terminal electrode for connecting the gate line or source line to external signal source is formed. Around the terminal forming area, a first metallic line and a second metallic line are extended below the terminal electrode. The first metallic line and the second metallic line are connected to the terminal electrode via respective contact holes. The first metallic line and the second metallic line are in different layers interposing an insulating layer therebetween.

Abstract: A liquid crystal display device having transistors disposed at the intersections of gate lines and source lines, pixel electrodes connected with the transistors, opposite electrodes opposite to these pixel electrodes, and liquid crystal held between said opposite electrodes and said pixel electrodes is disclosed. The pixel electrodes comprise a first pixel electrode and a second pixel electrode. The second pixel electrode are disposed in a layer above an insulating layer which is itself disposed in a layer above the first pixel electrode. The second pixel electrode has a region that does not overlap with the first pixel electrode. The second pixel electrode are electrically connected with the first pixel electrode.

Abstract: Parasitic capacity between Cs lines and source lines forming a pixel section is reduced, whereby characteristic resistant to crosstalk is achieved, aperture ratio is increased, and brightness of LCD is increased. The Cs lines are arranged on the source lines in such a manner as to cover the source lines, and pixel electrodes are arranged and formed on the Cs lines in such a manner as to partially overlap. By forming a structure in which the source lines, the Cs lines and the pixel electrodes are laminated in order, parasitic capacity between the Cs lines and the source lines forming a pixel section can be reduced, and crosstalk can be minimized. As a distance between the source lines and the pixel electrodes can be reduced from the viewpoint of a plan view, aperture ratio can be improved.

Abstract: Parasitic capacity between Cs lines and source lines forming a pixel section is reduced, whereby characteristic resistant to crosstalk is achieved, aperture ratio is increased, and brightness of LCD is increased. The Cs lines are arranged on the source lines in such a manner as to cover the source lines, and pixel electrodes are arranged and formed on the Cs lines in such a manner as to partially overlap. By forming a structure in which the source lines, the Cs lines and the pixel electrodes are laminated in order, parasitic capacity between the Cs lines and the source lines forming a pixel section can be reduced, and crosstalk can be minimized. As a distance between the source lines and the pixel electrodes can be reduced from the viewpoint of a plan view, aperture ratio can be improved.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: Parasitic capacity between Cs lines and source lines forming a picture element section is reduced, whereby characteristic resistant to crosstalk is achieved, opening ratio is increased, and brightness of LCD is increased.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: In a semiconductor memory device having a spare memory cell array and a spare column decoder and a spare row decoder as redundant circuits, redundancy detecting circuits for testing to see whether the redundant circuits are used or not after completion of the semiconductor memory device as a product are set so as to be capable of providing particular current signals or voltage signals, which indicate that the redundant circuits are used to predetermined external terminals, in response to an output signal at a predetermined logic level from a spare row decoder activating circuit or a spare column decoder activating circuit.

Abstract: An upper column address strobe signal and a lower column address strobe signal applied to a dynamic RAM are 180.degree. out of phase from each other. Data of n bits are read out from a memory cell array at a time. The data read out from memory cell array is divided into two bit groups and applied to an upper IO buffer and a lower IO buffer. Upper IO buffer and lower IO buffer latch sequentially the upper bit group and the lower bit group and output these groups to a data transmission bus in response to the upper column address strobe signal and the lower column address strobe signal.

Abstract: A substrate bias generating circuit including waveform shaping circuits for producing two signals having different phases on the basis of signals in phase extracted from a ring oscillator and two logic gates using these two signals having large phase difference as inputs is disclosed. A first charge pump circuit is driven with one of outputs of these two logic gates and a second charge pump circuit is driven by the other output. First charge pump circuit and second charge pump circuit are electrically coupled to generate substrate bias alternately. Since the difference in phase of two signals inputted to the two logic gates respectively is so large that a possibility is reduced of occurrence of a period in which both of input potential to charge pump circuit and input potential to charge pump circuit are at a low level even if a rise speed and a fall speed of input potential to charge pump circuit greatly differ from a fall speed and a rise speed of input potential to charge pump circuit, respectively.

Abstract: A substrate bias generating circuit improved for a DRAM is disclosed. The substrate bias generating circuit is driven by an externally applied signal /RAS, and a drive pulse signal is divided by a newly provided frequency division circuit. A ratio of division of the frequency division circuit is so set that power consumed by a substrate bias generating circuit is minimized under the requirement that a potential of a substrate of the DRAM should be kept within a permissible range. Therefore, a potential of the semiconductor substrate can be kept within a permissible range under less power consumption.

Abstract: A dynamic random access memory comprises a semiconductor substrate of a first conductivity type, a plurality of work lines, a plurality of bit lines, a plurality of active regions and a plurality of memory cells. The word lines extend in a first direction on a major surface of the semiconductor substrate. The bit lines are formed on the word lines and extend in a second direction intersecting with the first direction. The plurality of active regions are formed spaced apart at least at a predetermined interval in a third direction intersecting with the first and the second directions. Each of the active regions substantially forms a plane rectangle. The memory cells are arranged at intersection points of the word lines and the bit lines. Each memory cell comprises one and the other impurity regions of a second conductivity type, a gate electrode connected to the word lines, a storage node and a cell plate. The storage node is in contact with the other impurity region and is located above the bit line.