Abstract: The present invention relates to a MIS FET having an additional gate electrode (referred to as a suppression gate electrode) which extends along a boundary region between a MIS FET active region and a field oxide film under a drain wiring. When the drain wiring is supplied with a voltage high enough to induce an inversion layer of the same polarity as the MIS FET channel, a parasitic transistor is formed in parallel with the MIS FET and creates an increase in leakage current. A suppression gate electrode of the present invention forms an interrupting transistor connected in series with the parasitic transistor and therefore cuts off the leakage current.