Patents by Inventor Akio Niwa

Akio Niwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8125410
    Abstract: A test pattern generation circuit outputs a test pattern during a clock phase adjustment period. A flip-flop circuit latches the test pattern at the fall of a shift clock and outputs it as a test pattern. A latch miss detection circuit outputs a latch miss detection signal indicating presence/absence of a latch miss generation according to the test pattern and a delay shift clock. A clock phase controller delays the shift clock according to the latch miss detection signal, thereby outputting a delay shift clock.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: February 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazuhito Tanaka, Akio Niwa, Mitsuhiro Kasahara, Tadayuki Masumori, Mamoru Seike
  • Publication number: 20060220992
    Abstract: A test pattern generation circuit (100) outputs a test pattern (TP) during a clock phase adjustment period. A flip-flop circuit (110) latches the test pattern (TP) at the fall of a shift clock (SCK) and outputs it as a test pattern (Tpa). A latch miss detection circuit (130) outputs a latch miss detection signal (LM) indicating presence/absence of a latch miss generation according to the test pattern (TPa) and a delay shift clock (DSCK). A clock phase control section (120) delays the shift clock (SCK) according to the latch miss detection signal (LM), thereby outputting a delay shift clock (DSCK).
    Type: Application
    Filed: August 4, 2004
    Publication date: October 5, 2006
    Inventors: Kazuhito Tanaka, Akio Niwa, Mitsuhiro Kasahara, Tadayuki Masumori, Mamoru Seike
  • Patent number: 6876395
    Abstract: Video data of a field necessary for I/P conversion and scanning line conversion is stored in a field memory part (7), vertical frequency conversion is performed by a memory control processing part (2), I/P conversion is performed by an I/P conversion processing part (3), scanning line conversion is performed by a scanning line conversion part (4) and horizontal pixel conversion is performed by a horizontal pixel conversion processing part (5) with the data stored in the field memory part, and a synchronous processing part (6) supplies a prescribed clock, a horizontal synchronizing signal and a vertical synchronizing signal to each block. A single system performs vertical frequency conversion, I/P conversion, scanning line conversion and horizontal pixel conversion.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: April 5, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuaki Muto, Toshio Wakahara, Akio Niwa, Takuma Higashi, Tomoko Morita, Yuji Sekiguchi
  • Patent number: 6034656
    Abstract: The plasma display panel having brightness display ranges comprising a gradation brightness display range which displays gradation brightness corresponding to the input signals under a preset input signal level and a constant brightness display range which displays a constant peak brightness greater than the maximum brightness corresponding to input signals greater than the preset input signal level. The plasma display panel can provide the gradation display up to the maximum brightness corresponding to the input signals up to the maximum input and provide the constant peak brightness corresponding to the peak level input by adding one additional weighting bit for the higher gradation. Consequently, a high quality brightness display with high mean value of the brightness and sufficiently high peak brightness can be achieved. Furthermore, the plasma display panel enhances the brightness weighting value and the value of .gamma. for the reverse .gamma.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: March 7, 2000
    Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corporation
    Inventors: Kumetsugu Yamamoto, Yukiharu Ito, Akio Niwa, Takao Wakitani, Takuma Higashi
  • Patent number: 5221160
    Abstract: A disclosure is made of a subterranean connecting method and a connecting apparatus therefor which are suitable for use when two shield machines are used to excavate a pair of tunnel sections from both ends of a tunnel, and the tunnel sections are connected to each other in mid course. During underground connection, it is important to secure sealing and water retarding with respect to soil and water pressure exerted by the ground in the vicinity of the connecting section. For this purpose, in the connecting apparatus, a penetration ring is arranged in one of the shield machines, and a penetration chamber in which the penetration ring is accommodated is arranged in the other shield machine. Both the both shield machines face each other with a slight gap remaining therebetween and, subsequently, the penetration ring is moved forward and penetrates into the penetration chamber of the mating shield machine. By this penetration, the area between both the shield machines are closed by the penetration ring.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: June 22, 1993
    Assignees: Shimizuo Construction Co., Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Youji Azuma, Hisao Arai, Kazuo Isaka, Hiroyuki Kubo, Tohru Goto, Tokuharu Nakajima, Akihiro Honda, Kazuo Miyazawa, Toshio Watanabe, Yoshihiko Shimizu, Daizo Tanaka, Nobuhiro Tuchiya, Takao Nakagawa, Shigeteru Iba, Yoshihiro Ohishi, Masahiko Siguyama, Kichitaro Tsuji, Shigeru Nishitake, Akio Niwa