Patents by Inventor Akio Rokugawa

Akio Rokugawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366949
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 30, 2019
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Jun Furuichi, Akio Rokugawa, Takashi Ito
  • Patent number: 10028393
    Abstract: A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: July 17, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Akio Rokugawa
  • Publication number: 20180166372
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 14, 2018
    Inventors: Noriyoshi SHIMIZU, Yusuke GOZU, Jun FURUICHI, Akio ROKUGAWA, Takashi Ito
  • Patent number: 9875957
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 23, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Jun Furuichi, Akio Rokugawa, Takashi Ito
  • Patent number: 9820391
    Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 14, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Shoji Watanabe, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9735098
    Abstract: A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer formed on the upper surface of the insulation layer covering a lower side surface of the connection terminal, and a cover layer covering an upper side surface and an upper surface of the connection terminal exposed from the protective insulation layer. The protective insulation layer includes an upper surface defining a protrusion bulged upward around the connection terminal. The protrusion includes a peak, a first slope inclined downward from the peak and extending toward the connection terminal, and a second slope inclined downward from the peak and extending away from the connection terminal. The cover layer further covers the first slope, the peak, and a part of the second slope.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 15, 2017
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Akio Rokugawa
  • Publication number: 20170141023
    Abstract: A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer formed on the upper surface of the insulation layer covering a lower side surface of the connection terminal, and a cover layer covering an upper side surface and an upper surface of the connection terminal exposed from the protective insulation layer. The protective insulation layer includes an upper surface defining a protrusion bulged upward around the connection terminal. The protrusion includes a peak, a first slope inclined downward from the peak and extending toward the connection terminal, and a second slope inclined downward from the peak and extending away from the connection terminal. The cover layer further covers the first slope, the peak, and a part of the second slope.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 18, 2017
    Inventors: HIROMU ARISAKA, NORIYOSHI SHIMIZU, AKIO ROKUGAWA
  • Patent number: 9620446
    Abstract: A wiring board includes plural terminals, an insulating layer, and recess portions. Each terminal includes a roughened upper surface and a roughened side surface. The insulating layer is formed between the terminals. The upper surfaces of the terminals are exposed. An upper surface of the insulating layer is a concave curved surface. The recess portions are formed in the insulating layer around the terminals so as to partially expose the side surfaces of the terminals.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 11, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Hiromu Arisaka, Akio Rokugawa, Toshinori Koyama
  • Patent number: 9565775
    Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 7, 2017
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Hiromu Arisaka, Akio Rokugawa
  • Patent number: 9520352
    Abstract: A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating layer is formed with through holes. The first via wirings are formed in the through holes. The connection terminals are electrically connected to the first wiring layer through the first via wirings. The connection terminals protrude upward from the first insulating layer. The protection layer is made of insulating resin which contains photosensitive resin as a main component. The protection layer is formed on an upper surface of the first insulating layer. The protection layer includes first and second protection layers. The first protection layer surrounds the connection terminals. The second protection layer is separated from the first protection layer. The second protection layer is thinner than the first protection layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 13, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9455219
    Abstract: A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 27, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa, Toshinori Koyama
  • Patent number: 9380707
    Abstract: A method of manufacturing a wiring substrate includes: preparing a laminated plate of a metal layer and an insulating layer; adhering the laminated plate to a first support body facing the metal layer; and forming a first wiring layer with vias extending through the insulating layer and first pads exposed from a first surface of the insulating layer. The method also includes: separating a multilayer structure including the metal, insulating, and first wiring layer from the first support body; adhering the multilayer structure to a second support body facing the first wiring layer; removing the metal layer; forming a plurality of second wiring layers including second pads connected to the vias and exposed from a second surface of the insulating layer opposite the first surface; and separating the insulating, the first wiring, and the plurality of second wiring layers from the second support body, to obtain the wiring substrate.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: June 28, 2016
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa, Toshinori Koyama, Wataru Kaneda
  • Publication number: 20160174379
    Abstract: A wiring board includes plural terminals, an insulating layer, and recess portions. Each terminal includes a roughened upper surface and a roughened side surface. The insulating layer is formed between the terminals. The upper surfaces of the terminals are exposed. An upper surface of the insulating layer is a concave curved surface. The recess portions are formed in the insulating layer around the terminals so as to partially expose the side surfaces of the terminals.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 16, 2016
    Inventors: Noriyoshi Shimizu, Hiromu Arisaka, Akio Rokugawa, Toshinori Koyama
  • Publication number: 20160172287
    Abstract: A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating layer is formed with through holes. The first via wirings are formed in the through holes. The connection terminals are electrically connected to the first wiring layer through the first via wirings. The connection terminals protrude upward from the first insulating layer. The protection layer is made of insulating resin which contains photosensitive resin as a main component. The protection layer is formed on an upper surface of the first insulating layer. The protection layer includes first and second protection layers. The first protection layer surrounds the connection terminals. The second protection layer is separated from the first protection layer. The second protection layer is thinner than the first protection layer.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 16, 2016
    Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9257386
    Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 9, 2016
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Masato Tanaka, Tetsuya Koyama, Akio Rokugawa
  • Publication number: 20160020163
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 21, 2016
    Inventors: Noriyoshi SHIMIZU, Yusuke GOZU, Jun FURUICHI, Akio ROKUGAWA, Takashi Ito
  • Publication number: 20160007460
    Abstract: A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 7, 2016
    Inventors: Noriyoshi SHIMIZU, Yusuke GOZU, Akio ROKUGAWA
  • Patent number: 9220167
    Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 22, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Masato Tanaka, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9167692
    Abstract: A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 20, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
  • Publication number: 20150282307
    Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.
    Type: Application
    Filed: February 4, 2015
    Publication date: October 1, 2015
    Inventors: Noriyoshi SHIMIZU, Shoji WATANABE, Toshinori KOYAMA, Akio ROKUGAWA