Abstract: A semiconductor package of superior high frequency characteristics enabling easy mounting of a large-sized capacitor and thereby enabling fluctuation of the power supply voltage to be suppressed and enabling a reduction of the inductance of the wiring portion connecting the capacitor and a connection terminal, that is, a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, wherein the capacitor is comprised of, in an attachment hole passing through the board in the thickness direction, a conductor wire to be connected to a connection terminal of a semiconductor chip at one end, a high dielectric constant material covering the conductor wire at a predetermined thickness, and a conductor layer arranged between the outer circumference of the high dielectric constant material and the inner wall of the attachment hole, provided as a coaxial structure having the conductor wire at its center, and a method of production of the same.

Abstract: A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.

Abstract: In a process of manufacturing a core substrate of a semiconductor package using a metal core, through holes are formed in required positions on the metal core by an etching or a punching. Then, surfaces of the metal core inclusive of inner walls of the through holes are filled with insulative resin by an electrophoretic deposition process so as to form resin films. Thereafter, conductive thin films are formed on the entire surfaces of the resin films and the insides of the through holes are filled with a conductive material.

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract: To enable vias to be arranged at an improved density and ensure good electrical connection between conductor wiring patterns in the adjoining insulating layers, a process of producing a multilayer circuit board having multiple layers of conductor wiring patterns with insulating layers intervening therebetween, the insulating layers having vias extending therethrough to provide electrical connection between the conductor wiring patterns, the process comprising the steps of: providing a circuit board having a conductor wiring pattern formed on one side thereof; forming an insulating layer covering the conductor wiring pattern and said one side of the circuit board; forming a viahole extending through the insulating layer to the conductor wiring pattern, the viahole having a bottom defined by an exposed portion of the conductor wiring pattern; forming a recess in the insulating layer, the recess extending from an orifice of the viahole in the same pattern as another conductor wiring pattern which will be formed

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract: A process for making a multilayer wiring board includes the following steps of: laminating an electrically insulating resin substrate, having first and second surfaces and a metal layer formed on the first surface, onto a base material on which a predetermined wiring pattern is formed, so that the second surface of the resin substrate is adhered to the base material; removing a predetermined amount of the metal layer to form an opening at a position where a connection with the wiring pattern is to be provided; irradiating a laser beam toward the resin layer through the resin removed region to form a blind via hole having a diameter smaller than that of the opening, so that the wiring pattern is exposed at a bottom of the blind via hole; electroless plating to form an electroless plated film on the exposed wiring pattern, a side wall of the blind via hole, a step portion of the exposed resin layer, and at least a metal layer at a periphery of the opening; electro plating to form an electro plated film on the e

Abstract: A resin plate having wiring pattern recesses and via through holes is made. All of the surfaces of the resin plate including inner walls of said wiring pattern recesses and via through holes are coated with a metal film. An electroplating is applied using the metal film as a power-supply layer to fill a plated metal into the wiring pattern recesses and via through holes. The metal film formed on the resin plate except for the inner walls of the wiring pattern recesses and via through holes is removed, so that wiring pattern and via are exposed on a surface the same as that of the resin plate.

Abstract: A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on t

Abstract: A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on t

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract: A charged particle emission source structure comprising a needle-like electrode for emission of charged particles, a reservoir for a liquid metal for wetting the surface of the needle-like electrode, heat-generating support members for heating the liquid metal and holding the reservoir or the needle-like electrode, and an extraction electrode for applying an electric field as between it and the needle-like electrode, which is characterized in that conductive partitions hardly wettable with the liquid metal are provided between the heat-generating support members and the reservoir or the needle-like electrode.