Abstract: A demodulator for wobble signals or other phase-modulated signals that can reduce demodulation errors due to superimposition of noise, as well as a data recording/reproduction device that contains said demodulator. In the signal range of the bit signal obtained by insertion synchronously with detected bit synchronization signal Bsync, prescribed sign operations are performed on integration values S2 of the wobble signals during periods where phase changes of bit signals should take place, respectively, and the results are summed so as to compute characteristic quantities S13 and S16 of the bit signals “1” and “0,” respectively. On the basis of the result of the comparison of the characteristic quantities, the value of the bit signal corresponding to bit synchronization signal Bsync is determined.

Abstract: A method and circuitry for testing a memory to determine its column address organization are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes a controllable multiplexer that selects certain combinations of address bits for use as column address bits to be applied to the memory; the selection of the multiplexer is controlled by the contents of a memory array type register associated with the memory or memory bank. In operation, a first data word is written to memory using a first address, and a second data word is written to memory using a second address that is spaced apart from the first address by a specified increment related to a trial number of column address bits of the memory.

Abstract: A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit.

Abstract: An electronic system, such as a computer system, having a first level write through cache and a smaller second-level write-back cache, is disclosed. The disclosed computer system includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, and first and second level caches. The microprocessor unit is connected to external dynamic random access memory (DRAM). The first level cache is a write-through cache, while the second level cache is a write-back cache that is much smaller than the first level cache. In operation, a write access cache miss to the first level cache that is a cache hit in the second level cache effects a write to the second level cache, rather than to DRAM, thus saving a wait state. A dirty bit is set for each modified entry in the second level cache. Upon the second level cache being full of modified data, a cache flush to DRAM is automatically performed.

Abstract: A method and circuitry for generating column addresses for a memory based upon signals on an address bus in a computer system, are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access memory (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache.

Abstract: An electronic system, such as a computer system, in which access to configuration registers used by a memory controller, is selectively enabled. The disclosed system includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, a bus bridge circuit, and configuration registers. The microprocessor unit is connected to external dynamic random access memory (DRAM). The memory controller circuit is operable to perform an operation utilizing current information in one or more of the configuration registers. The bus bridge circuit includes a request logic circuit for supplying a request output signaling an impending access to one or more of the configuration registers. The memory controller circuit includes a reply logic circuit for supplying a reply output back to the request logic circuit after the operation utilizing current configuration register information is completed.

Abstract: An electronic device for use in a computer system, and having a small second-level write-back cache, is disclosed. The device may be implemented into a single integrated circuit, as a microprocessor unit, to include a microprocessor core, a memory controller circuit, and first and second level caches. In a system implementation, the device is connected to external dynamic random access memory (DRAM). The first level cache is a write-through cache, while the second level cache is a write-back cache that is much smaller than the first level cache. In operation, a write access that is a cache hit in the second level cache writes to the second level cache, rather than to DRAM, thus saving a wait state. A dirty bit is set for each modified entry in the second level cache. Upon the second level cache being full of modified data, a cache flush to DRAM is automatically performed. In addition, each entry of the second level cache is flushed to DRAM upon each of its byte locations being modified.

Abstract: A method and circuitry for testing a memory in a computer system, to determine the sizes of individual memory banks, is disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for enabling the selection of an individual memory bank of a memory, such as dynamic random access memory, which is arranged as multiple banks of arbitrary size. In operation, a memory bank is selected, and a first data word is written to the bottom memory address of the bank (which, for banks other than the first bank, is the top memory address of the previous bank). A second data word is written to a second memory location that is spaced apart from the bottom address by a trial value of the bank size.

Abstract: An electronic system including circuitry for generating column addresses for a memory in the system, based upon signals on an address bus in the system, is disclosed. The disclosed system includes a microprocessor unit having a memory controller unit, within which circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type, is provided. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache.

Abstract: An electronic device and a method of operating the same to control access to configuration registers used by a memory controller, are disclosed. The disclosed device includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, a bus bridge circuit, and configuration registers. The microprocessor unit is connected to external dynamic random access memory (DRAM). The memory controller circuit is operable to perform an operation utilizing current information in one or more of the configuration registers. The bus bridge circuit includes a request logic circuit for supplying a request output signaling an impending access to one or more of the configuration registers. The memory controller circuit includes a reply logic circuit for supplying a reply output back to the request logic circuit after the operation utilizing current configuration register information is completed.