Patents by Inventor Akio Shimoyama

Akio Shimoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11454601
    Abstract: A substrate evaluation chip is used to perform a test for evaluating a thermal characteristic of a mounting substrate that is mountable a power semiconductor. The substrate evaluation chip includes an insulating substrate bonded with the mounting substrate, and a heating pattern that is formed on a surface of the insulating substrate by a metallic film and is arranged by having a predetermined shape that is optimized to beat the insulating substrate more uniformly. The insulating substrate is a substrate in which an insulating film is formed on a surface of a single crystal substrate having a thermal conductivity of 250 [W/mK] or more.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: September 27, 2022
    Assignees: OSAKA UNIVERSITY, YAMATO SCIENTIFIC CO., LTD.
    Inventors: Katsuaki Suganuma, Shijo Nagao, Akio Shimoyama, Dongjin Kim, Kazutaka Takeshita, Naoki Wakasugi
  • Patent number: 11049840
    Abstract: A bonding device (100) bonds at least one component (C) to a substrate (B) using a metal material (M). The bonding device (100) includes a wall section (20), at least one pressing section (40), and a rotational shaft (30). The rotational shaft (30) is fixed to the wall section (20). Each pressing section (40) has an arm (42) and a presser (43) or a substrate supporting member (90). The arm (42) extends from the rotational shaft (30). The arm (42) pivots about the rotational shaft (30). The presser (43) presses the component (C). The substrate supporting member (90) is disposed on a reference surface (142). The substrate supporting member (90) supports the substrate (B). The component (C) is bonded to the substrate (B) through point contact of the presser (43) with the component (C) or point contact of the substrate supporting member (90) with the reference surface (142).
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 29, 2021
    Assignee: OSAKA UNIVERSITY
    Inventors: Katsuaki Suganuma, Shijo Nagao, Akio Shimoyama, Shinya Seki
  • Publication number: 20200378912
    Abstract: A substrate evaluation chip is used to perform a test for evaluating a thermal characteristic of a mounting substrate that is mountable a power semiconductor. The substrate evaluation chip includes an insulating substrate bonded with the mounting substrate, and a heating pattern that is formed on a surface of the insulating substrate by a metallic film and is arranged by having a predetermined shape that is optimized to beat the insulating substrate more uniformly. The insulating substrate is a substrate in which an insulating film is formed on a surface of a single crystal substrate having a thermal conductivity of 250 [W/mK] or more.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 3, 2020
    Applicants: OSAKA UNIVERSITY, YAMATO SCIENTIFIC CO., LTD.
    Inventors: Katsuaki Suganuma, Shijo Nagao, Akio Shimoyama, Dongjin Kim, Kazutaka Takeshita, Naoki Wakasugi
  • Publication number: 20190189587
    Abstract: A bonding device (100) bonds at least one component (C) to a substrate (B) using a metal material (M). The bonding device (100) includes a wall section (20), at least one pressing section (40), and a rotational shaft (30). The rotational shaft (30) is fixed to the wall section (20). Each pressing section (40) has an arm (42) and a presser (43) or a substrate supporting member (90). The arm (42) extends from the rotational shaft (30). The arm (42) pivots about the rotational shaft (30). The presser (43) presses the component (C). The substrate supporting member (90) is disposed on a reference surface (142). The substrate supporting member (90) supports the substrate (B). The component (C) is bonded to the substrate (B) through point contact of the presser (43) with the component (C) or point contact of the substrate supporting member (90) with the reference surface (142).
    Type: Application
    Filed: June 16, 2017
    Publication date: June 20, 2019
    Applicant: OSAKA UNIVERSITY
    Inventors: Katsuaki SUGANUMA, Shijo NAGAO, Akio SHIMOYAMA, Shinya SEKI
  • Patent number: 7605057
    Abstract: A method of manufacturing a semiconductor device can suppress the generation of burrs when an array of integrated circuits to which a supporting member is bonded for assistance is separated into chips. The supporting member having thinned regions (or void regions which are openings in the supporting member) located correspondingly beneath the scribing lines extending between the integrated circuits is bonded by an adhesive to the back side of a semiconductor substrate on which integrated circuits are arrayed at the primary side. Then, a dicing tape is attached to the support member to secure the entire assembly, and the assembly of the integrated circuits, the semiconductor substrate, the adhesive, and the supporting member are cut along the scribing lines, and then the dicing tape is removed.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: October 20, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akio Shimoyama, Hajime Oda, Keiichi Sawai, Takayuki Taniguchi
  • Patent number: 7364664
    Abstract: The present processing apparatus blocks off such a portion of a flow of a plating solution (17) that is other than a vicinity of a liquid surface, by using a first partition plate (15) whose lower end is in close contact with a bottom of a plating tank (11) and whose upper end is at a position lower than a liquid surface. Therefore, the plating solution (17) flowing at the bottom of the plating tank (11) flows upwards along the first partition plate (15). At this time, heavy foreign substances do not tend to follow such an upward movement of the plating solution (17), and therefore sink and accumulate in a vicinity of the lower end of the first partition plate (15), so as not to flow into a downstream side of the plate. With this arrangement, the present processing apparatus can remove the heavy foreign substances from the plating solution (17) without relying solely on a filter of a circulation pipe (10).
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: April 29, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akio Shimoyama, Kazushi Kodama
  • Publication number: 20080094714
    Abstract: The present invention provides a green mirror having both glare proof property and pollution preventive property and furthermore an excellent visibility by controlling the spectral reflection spectrum of the mirror comprising a photo catalyst titanium oxide layer. The mirror comprises a glass substrate, a reflection film, and a composite film with a colored layer, a titanium oxide layer and a silicon oxide layer laminated sucessively, wherein the spectral reflectance peak is 490 to 540 nm.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 24, 2008
    Inventors: Hironori Shibasaki, Shigeru Morohashi, Tsutomu Ubukata, Akio Shimoyama
  • Publication number: 20080032485
    Abstract: A method of manufacturing a semiconductor device can suppress the generation of burrs when an array of integrated circuits to which a supporting member is bonded for assistance is separated into chips. The supporting member having thinned regions (or void regions which are openings in the supporting member) located correspondingly beneath the scribing lines extending between the integrated circuits is bonded by an adhesive to the back side of a semiconductor substrate on which integrated circuits are arrayed at the primary side. Then, a dicing tape is attached to the support member to secure the entire assembly, and the assembly of the integrated circuits, the semiconductor substrate, the adhesive, and the supporting member are cut along the scribing lines, and then the dicing tape is removed.
    Type: Application
    Filed: July 5, 2007
    Publication date: February 7, 2008
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Akio Shimoyama, Hajime Oda, Keiichi Sawai, Takayuki Taniguchi
  • Publication number: 20040232091
    Abstract: The present processing apparatus blocks off such a portion of a flow of a plating solution (17) that is other than a vicinity of a liquid surface, by using a first partition plate (15) whose lower end is in close contact with a bottom of a plating tank (11) and whose upper end is at a position lower than a liquid surface. Therefore, the plating solution (17) flowing at the bottom of the plating tank (11) flows upwards along the first partition plate (15). At this time, heavy foreign substances do not tend to follow such an upward movement of the plating solution (17), and therefore sink and accumulate in a vicinity of the lower end of the first partition plate (15), so as not to flow into a downstream side of the plate. With this arrangement, the present processing apparatus can remove the heavy foreign substances from the plating solution (17) without relying solely on a filter of a circulation pipe (10).
    Type: Application
    Filed: January 23, 2004
    Publication date: November 25, 2004
    Inventors: Akio Shimoyama, Kazushi Kodama
  • Patent number: 5197650
    Abstract: A die bonding apparatus includes a device for making a coarse surface in a region where an identifier is to be applied to a lead frame; an application device for applying the identifier to the coarse surface region, a dividing device for dividing a wafer into chips, a test device for testing the wafer which has not been divided into chips yet in positions corresponding to the prospective chips, a storage device for storing information about positions of the chips on the wafer and the test results, a die bonding device picking out the chips from the wafer for die-bonding them to the lead frame having the identifier, a reading device for reading the identifier of the lead frame to which the chips are to be die-bonded, an information processing device for adding information which the identifier contains to the test results and position information about each of the chips to make test information, and an output device for outputting the test information.
    Type: Grant
    Filed: April 2, 1992
    Date of Patent: March 30, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiko Monzen, Akio Shimoyama, Noriki Iwasaki
  • Patent number: 5173147
    Abstract: An apparatus for sealing a semiconductor package, which is used for performing a sealing operation, includes a unit for emitting ultraviolet rays, and a package base having an entrance surface and an exit surface. The package base between the entrance surface and the exit surface is made of quartz glass. The emitting means closely contacts the entrance surface. And ultraviolet rays emitting by the emitting unit are applied through the quartz glass to the semiconductor package which is mounted on the exit surface.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: December 22, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akio Shimoyama, Kouki Kitaoka, Noriki Iwasaki