Abstract: There is provided an optimization apparatus that reduces the time required to create a delivery plan. An optimization apparatus (100) includes an acquisition unit (110) that acquires delivery information regarding each of one or more products for each of a plurality of consumption locations, an identification unit (120) that identifies a plurality of delivery task candidates departing from a delivery source, delivering the one or more products to each of one or more consumption locations, and returning to the delivery source, a determination unit (130) that determines, based on the delivery information, at least one of evaluation values and a vehicle type of a delivery vehicle for each candidate, and a selection unit (140) that selects a plurality of delivery tasks from the plurality of identified candidates based on a result of optimizing an objective function based on a determination result.

Abstract: The present invention relates to a negative electrode material for secondary batteries, comprising graphite; wherein the graphite comprises hexagonal crystal graphite and rhombohedral crystal graphite, and has a low-crystalline carbon coating on a surface thereof; and the graphite has exothermic peaks in the range of 600° C. or lower and in the range of 690° C. or higher in DTA measurement, or the graphite has a full width at half maximum of a (101) peak of the hexagonal crystal graphite of 0.2575° or less in XRD measurement, or the graphite has an absolute value of the difference between the lattice strain obtained from (101) plane spacing of the hexagonal crystal graphite and the lattice strain obtained from (100) plane spacing of the hexagonal crystal graphite of 7.1×10?4 or less in XRD measurement.

Abstract: The mechanical strength of an electrode sheet becomes problematic when employing means for improving the productivity of an electrode process. In a collector aluminum foil of the present invention, when the intensities of the (022) and (111) diffraction peaks appearing in an XRD spectrum measured in the reflection geometry are denoted by IB(022) and IB(111), respectively, a value of IB(022)/IB(111) is 200 or less.

Abstract: There is provided a negative electrode material for lithium ion secondary batteries having a structure in which in charged and discharged states, a LixSi compound (2) exists in the inside of a Li oxide (1) and the LixSi compound is dispersed in the inside of the Li oxide. The negative electrode material, in which volume change resulting from charge/discharge is suppressed, has excellent performance as a negative electrode material for lithium ion secondary batteries.

Abstract: An object is to provide means, which is capable of performing quality management with sufficient precision even in a case where the thickness of an amorphous carbon layer is small, as quality management means for a negative electrode active material of a lithium-ion secondary battery including an amorphous carbon layer on a surface. Provided is a quality management method for a negative electrode active material of a lithium-ion secondary battery which includes an amorphous carbon layer on a surface. In the quality management method, an aspect of a change in a plurality of D/G ratios, which are obtained by performing a first process of heating an inspection object at a predetermined heating temperature, and of measuring each of the D/G ratios through Raman scattering spectroscopy measurement a predetermined number of times while changing the heating temperature, is set as an index of the quality management.

Abstract: The present invention relates to a negative electrode material for secondary batteries, comprising graphite; wherein the graphite comprises hexagonal crystal graphite and rhombohedral crystal graphite, and has a low-crystalline carbon coating on a surface thereof; and the graphite has exothermic peaks in the range of 600° C. or lower and in the range of 690° C. or higher in DTA measurement, or the graphite has a full width at half maximum of a (101) peak of the hexagonal crystal graphite of 0.2575° or less in XRD measurement, or the graphite has an absolute value of the difference between the lattice strain obtained from (101) plane spacing of the hexagonal crystal graphite and the lattice strain obtained from (100) plane spacing of the hexagonal crystal graphite of 7.1×10?4 or less in XRD measurement.

Abstract: A downsized, low-power electro-optical modulator that achieves reducing both of the additional resistance in the modulation portion and the optical loss each caused by electrodes at the same time is provided. The electro-optical modulator includes a rib waveguide formed by stacking a second semiconductor layer 9 having a different conductivity type from a first semiconductor layer 8 on the first semiconductor layer 8 via a dielectric film 11, and the semiconductor layers 8 and 9 are connectable to an external terminal via highly-doped portions 4 and 10, respectively. In a region in the vicinity of contact surfaces of the semiconductor layers 8 and 9 with the dielectric film 11, a free carrier is accumulated, removed, or inverted by an electrical signal from the external terminal, and whereby a concentration of the free carrier in an electric field region of an optical signal is modulated, so that a phase of the optical signal can be modulated.

Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.

Abstract: An optical modulation structure includes a lower cladding layer (102), a first silicon layer (103) integrally formed from silicon of a first conductivity type on the lower cladding layer (102) while including a core (104) and slab regions (105) arranged on both sides of the core (104) and connected to the core, a concave portion (104a) formed in an upper surface of the core (104), and a second silicon layer (109) of a second conductivity type formed on a dielectric layer (108) in the concave portion (104a) so as to fill the concave portion (104a).

Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.

Abstract: A downsized, low-power electro-optical modulator that achieves reducing both of the additional resistance in the modulation portion and the optical loss each caused by electrodes at the same time is provided. The electro-optical modulator includes a rib waveguide formed by stacking a second semiconductor layer 9 having a different conductivity type from a first semiconductor layer 8 on the first semiconductor layer 8 via a dielectric film 11, and the semiconductor layers 8 and 9 are connectable to an external terminal via highly-doped portions 4 and 10, respectively. In a region in the vicinity of contact surfaces of the semiconductor layers 8 and 9 with the dielectric film 11, a free carrier is accumulated, removed, or inverted by an electrical signal from the external terminal, and whereby a concentration of the free carrier in an electric field region of an optical signal is modulated, so that a phase of the optical signal can be modulated.

Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Abstract: The components are a lower clad layer (102), a first silicon layer (103) that is formed on the lower clad layer (102) as a single body made of silicon of a first conduction type and has a slab region (105) that is disposed at a core (104) and on both sides of the core (104) and connects to the core, a concave section (104a) that is formed in the top surface of the core (104), and a second silicon layer (109) of a second conduction type that is formed inside the concave section (104a) with an intervening dielectric layer (108) to fill the inside of the concave section (104a).

Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Abstract: According to one embodiment, a disk device includes a disk, a drive section which is configured to support and rotate the disk, a head, and a head actuator assembly. The head actuator assembly includes a board unit including a base portion on which an electronic component is mounted, a main flexible printed circuit board which is configured to extend from the base portion and have a connecting end portion attached to the carriage, and a reinforcing plate including a bent portion fixed to the main flexible printed circuit board, and a vibration damper which is configured to include a sheet-shaped viscoelastic material stuck on the bent portion and a sheet-shaped reinforcing material, more rigid than the viscoelastic material and stuck on the viscoelastic material in superposed relation, and suppress vibration of the reinforcing plate.

Abstract: A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is not more than 1 micrometer, and a gate length that is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the sourced/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.

Abstract: An inertia latch mechanism has a latch arm, which latches a head actuator in a retreated position, and an inertia arm, which is rockably supported around a second pivot and rotates the latch arm to a latch position by rotating around the second pivot when subjected to an external force. A voice coil motor has a lower yoke, a top yoke, a voice coil attached to the head actuator and situated between the yokes, and a permanent magnet provided on at least one of the yokes. The top yoke has an arm retaining portion which extends overlapping the second pivot and that part of the inertia arm which is situated near the second pivot and restrains the inertia arm from slipping off the second pivot. The arm retaining portion is stepped to be one level higher than the top yoke.

Abstract: While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation regions, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.

Abstract: While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation region, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film comprising the silicon oxide film only.

Abstract: A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.