Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.

Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.

Abstract: A semiconductor device includes a first node receiving an external voltage, a second node receiving a grounding voltage, a protection circuit, and a device to be protected coupled in parallel between the first and second nodes, in which the protection circuit includes a lateral IGBT having an emitter coupled to the second node and an avalanche diode having an anode coupled to the collector of the lateral IGBT and a cathode coupled to the first node, and a clamp driving circuit coupled between the first and second nodes, and coupled to the gate of the lateral IGBT.

Abstract: A semiconductor device includes a first node receiving an external voltage, a second node receiving a grounding voltage, a protection circuit, and a device to be protected coupled in parallel between the first and second nodes, in which the protection circuit includes a lateral IGBT having an emitter coupled to the second node and an avalanche diode having an anode coupled to the collector of the lateral IGBT and a cathode coupled to the first node, and a clamp driving circuit coupled between the first and second nodes, and coupled to the gate of the lateral IGBT.

Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.

Abstract: A semiconductor device has a surge protection circuit electrically connected to a signal input terminal and including a diode and a transistor. The diode has its cathode region constituted of an n+ diffusion layer, an n? epitaxial layer, an n-type diffusion layer and an n+ diffusion layer. The n+ diffusion layer is electrically connected to a conductive layer and formed at a main surface of a semiconductor substrate. The n+ diffusion layer constitutes, together with a p-type diffusion layer, a pn junction where Zener breakdown occurs, and the pn junction with the Zener breakdown occurring therein is distant from a field oxide film. Then, the semiconductor device with the surge protection circuit without suffering from current leakage and thus normally operating can be achieved.

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings formed on the second insulating film and connected to the resistor film, in which a thickness T3 of the second insulating film is thinner than a thickness T2 of the resistor film.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: A semiconductor device has a surge protection circuit electrically connected to a signal input terminal and including a diode and a transistor. The diode has its cathode region constituted of an n+ diffusion layer, an n− epitaxial layer, an n-type diffusion layer and an n+ diffusion layer. The n+ diffusion layer is electrically connected to a conductive layer and formed at a main surface of a semiconductor substrate. The n+ diffusion layer constitutes, together with a p-type diffusion layer, a pn junction where Zener breakdown occurs, and the pn junction with the Zener breakdown occurring therein is distant from a field oxide film. Then, the semiconductor device with the surge protection circuit without suffering from current leakage and thus normally operating can be achieved.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: Isolation regions, a peripheral anode, an N-type island region for output and a passive N-type island region are formed at the main surface of a P− substrate. A dummy N-type island region is formed at a region located between two isolation regions. A P-type region is formed at the surface of this N well. A pair of N++ type regions are formed at the surface of P-type region. A gate electrode is formed on a portion of P-type region interposed between N++ type regions. N++ type region is connected to ground while N++ type region is electrically connected to isolation region. Accordingly, current is restricted from flowing between the N-type island region for output and the passive N-type island region so as to obtain a semiconductor device in which occurrence of malfunctions is prevented.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: Isolation regions, a peripheral anode, an N-type island region for output and a passive N-type island region are formed at the main surface of a P− substrate. A dummy N-type island region is formed at a region located between two isolation regions. A P-type region is formed at the surface of this N well. A pair of N++ type regions are formed at the surface of P-type region. A gate electrode is formed on a portion of P-type region interposed between N++ type regions. N++ type region is connected to ground while N++ type region is electrically connected to isolation region. Accordingly, current is restricted from flowing between the N-type island region for output and the passive N-type island region so as to obtain a semiconductor device in which occurrence of malfunctions is prevented.

Abstract: To improve resistance to instantaneous surge power of semiconductor devices having resistor films. The semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings and formed on the second insulating film and connected to the resistor film, in which a thickness T3 of the second insulating film is thinner than a thickness T2 of the resistor film.

Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.- silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Abstract: A power switching device which decreases both surge voltage and switching loss. As the inductor is connected to the emitter electrode of the IGBT element, the potential of the emitter electrode changes in the direction in which the IGBT element maintains the ON state with the attenuation of the main current when the IGBT element turns OFF from ON. Furthermore, as the inductor is included in the path of the OFF driving current for bringing the IGBT element to OFF, the OFF driving current once raises and then decreases. As a result, because the transition from ON to OFF calmly proceeds, the occurrence of the surge voltage is suppressed. On the other hand, since the inductor is not included in the path of the ON driving current, the transition from OFF to ON of the IGBT element is rapidly made. Accordingly, the switching loss occurring in the transition period is decreased. The decrease in the surge voltage and the decrease in the switching loss are compatibly realized.

Abstract: An n type diffusion region and a p type diffusion region are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate. A p type well is formed in the n- and p-type diffusion regions nearer the first main surface. A source n.sup.+ diffusion region is formed at the first main surface within the p type well. A gate electrode layer is formed opposite to the p type well sandwiched between the n type diffusion region and the source n.sup.+ diffusion region with a gate insulating layer disposed therebetween. The n- and p-type diffusion regions each have an impurity concentration distribution diffused from a sidewall surface of a trench. Thus, a fine, micron-order pn repeat structure can be achieved with sufficient precision and a high breakdown voltage semiconductor device is thus obtained which has superior on-state voltage and breakdown voltage as well as fast switching characteristics.

Abstract: Internal gate electrodes (71) are all connected in common to a gate terminal, and a floating gate electrode (72) is connected to the gate electrode of an NMOS transistor (M1). An external emitter electrode (91) is provided on a first major surface of P-type diffused lease region (21), and N-type diffused emitter region (31) and P-type diffused base region (21) are short-circuited. The source of the NMOS transistor (M1) and an emitter terminal are also connected to the external emitter electrode (91). The drain of the NMOS transistor (M1) is connected to an external terminal.

Abstract: An n type diffusion region and a p type diffusion region are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate. A p type well is formed in the n- and p-type diffusion regions nearer the first main surface. A source n.sup.+ diffusion region is formed at the first main surface within the p type well. A gate electrode layer is formed opposite to the p type well sandwiched between the n type diffusion region and the source n.sup.+ diffusion region with a gate insulating layer disposed therebetween. The n- and p-type diffusion regions each have an impurity concentration distribution diffused from a sidewall surface of a trench. Thus, a fine, micron-order pn repeat structure can be achieved with sufficient precision and a high breakdown voltage semiconductor device is thus obtained which has superior on-state voltage and breakdown voltage as well as fast switching characteristics.