Patents by Inventor Akio Uenisi

Akio Uenisi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6307246
    Abstract: A semiconductor substrate has a first main surface with a plurality of trenches 5a sandwiching a region in which p and n diffusions regions 2 and 3 are formed to provide a p-n junction along the depth of the trenches. P diffusion region 2 has a doping concentration profile provided by a p dopant diffused from a sidewall surface of one trench 5a, and n diffusion region 3 has a doping concentration profile provided by an n dopant diffused from a sidewall surface of the other trench 5a. A heavily doped n+ substrate region 1 is provided at a second main surface side of p and n diffusion regions 2 and 3. A depth Ld of trench 5a from the first main surface is greater than a depth Nd of p and n diffusion regions 2, 3 from the first main surface by at least a diffusion length L of the p dopant in p diffusion region 2 or the n dopant in n diffusion region 3 in manufacturing the semiconductor device. A high withstand voltage and low ON-resistance semiconductor device can thus be obtained.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: October 23, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Nitta, Tadaharu Minato, Akio Uenisi