Abstract: A friction stir welding method welds at least two members to be welded by overlapping the members to be welded and moving a welding tool. The friction stir welding method has a step of forming a closed space at a terminal end of a welding line which is a movement track of the welding tool, and a step of moving the welding tool to inside the closed space and pulling out the welding tool from the members to be welded.

Abstract: A battery case includes a refrigerant flow path formed by welding case members at mating surfaces and by covering them with a cover plate. Each of the case members includes a first convex portion extending flatly along a flow direction, a second convex portion extending flatly in a direction orthogonal to the flow direction at a position of the mating surfaces, and a concave portion. The first and second convex portion intersect with each other flatly without a step. The cover plate includes a concave portion and a convex portion extending flatly without a step along the flow direction. The refrigerant flow path is formed by welding the first convex portions and the convex portion and includes a first space between the concave portions of the case members and of the cover plate, and a second space between the second convex portions and the concave portion of the cover plate.

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.

Abstract: An auxiliary current source is provided that includes MOS transistors feeding startup auxiliary current to the input portion of an output common mode voltage generation circuit amplifying the output of a differential amplifier and generating an output common voltage, and a correction current source is provided that includes MOS transistors feeding correction current corresponding to the auxiliary current to a common mode feedback comparator. Thereby, a control loop that controls the output common voltage to a predetermined voltage even when the input of the differential amplifier is outside the dynamic range at the beginning is correctly started up, thereby stabilizing the output common voltage at a desired voltage.

Abstract: A digital analog converter includes a current conversion section and a voltage conversion section. The current conversion section has a first output terminal and a second output terminal. The first output terminal outputs a first current and a second output terminal outputs a second current, the first current varying in value according to inputted digital data, the sum of the first current and the second current becoming a constant current. The voltage conversion section converts the first current to a corresponding first voltage and produces an offset voltage on the basis of the constant current and outputs the sum of the first voltage and the offset voltage as an output voltage.

Abstract: Four input nodes I1-I4 for inputting 4-phase signals, four resistors R1-R4, four capacitors C1-C4, and four output nodes O1-O4 for outputting 4-phase signals are provided. The resistors and the capacitors are connected alternately in a loop, and the input nodes and output nodes are connected alternately to the respective nodes between the resistors and the capacitors sequentially. Each of the four resistors is composed of a group of three or more partial resistors, and three groups of the partial resistors R2a-R2c, R3a-R3c and R4a-R4c are collected respectively and arranged in the same attitude, while the partial resistors R1a-R1c of the remaining group are distributed into the other groups and arranged in the same line the same attitude as the partial resistors of each of the other groups. The regions of the thus collected groups are arranged in one direction.

Abstract: An auxiliary current source is provided that includes MOS transistors feeding startup auxiliary current to the input portion of an output common mode voltage generation circuit amplifying the output of a differential amplifier and generating an output common voltage, and a correction current source is provided that includes MOS transistors feeding correction current corresponding to the auxiliary current to a common mode feedback comparator. Thereby, a control loop that controls the output common voltage to a predetermined voltage even when the input of the differential amplifier is outside the dynamic range at the beginning is correctly started up, thereby stabilizing the output common voltage at a desired voltage.

Abstract: A digital analog converter includes a current conversion section and a voltage conversion section. The current conversion section has a first output terminal and a second output terminal. The first output terminal outputs a first current and a second output terminal outputs a second current, the first current varying in value according to inputted digital data, the sum of the first current and the second current becoming a constant current. The voltage conversion section converts the first current to a corresponding first voltage and produces an offset voltage on the basis of the constant current and outputs the sum of the first voltage and the offset voltage as an output voltage.

Abstract: In a differential amplifier and an operational amplifier each for amplifying a signal, a differential signal composed of first and second signals is inputted to a couple of input terminals (1, 2). When the voltage of the first signal is, e.g., less than the voltage value of a reference voltage source (15), a comparator (13) senses it and a switch circuit (12) switches to a first current source (6) and a current from a third current source (11) flows into the first current source (6) so that a current is inhibited from flowing in the first differential couple (4). As a result, the inputted differential signal is amplified and outputted only through a second differential couple (5). In a situation in which the voltage of the first signal exceeds the voltage of the reference voltage source (15), on the other hand, the switch circuit (12) switches to a current source (7) so that the inputted differential signal is amplified and outputted only through the first differential couple (4).

Abstract: In a differential amplifier and an operational amplifier each for amplifying a signal, a differential signal composed of first and second signals is inputted to a couple of input terminals (1, 2). When the voltage of the first signal is, e.g., less than the voltage value of a reference voltage source (15), a comparator (13) senses it and a switch circuit (12) switches to a first current source (6) and a current from a third current source (11) flows into the first current source (6) so that a current is inhibited from flowing in the first differential couple (4). As a result, the inputted differential signal is amplified and outputted only through a second differential couple (5). In a situation in which the voltage of the first signal exceeds the voltage of the reference voltage source (15), on the other hand, the switch circuit (12) switches to a current source (7) so that the inputted differential signal is amplified and outputted only through the first differential couple (4).

Abstract: An intermediate-frequency signal from a frequency mixer is subjected to channel selection by a band-pass filter. Then an output signal from the band-pass filter is subjected to analog-to-digital conversion by an analog-to-digital converter on a predetermined sampling frequency. An anti-aliasing filter is provided at a stage previous to the analog-to-digital converter. The anti-aliasing filter includes notch filters and attenuates signals with frequencies which are higher and lower than a frequency which is an integral multiple of the sampling frequency by the intermediate frequency.

Abstract: In a differential amplifier and an operational amplifier each for amplifying a signal, a differential signal composed of first and second signals is inputted to a couple of input terminals (1, 2). When the voltage of the first signal is, e.g., less than the voltage value of a reference voltage source (15), a comparator (13) senses it and a switch circuit (12) switches to a first current source (6) and a current from a third current source (11) flows into the first current source (6) so that a current is inhibited from flowing in the first differential couple (4). As a result, the inputted differential signal is amplified and outputted only through a second differential couple (5). In a situation in which the voltage of the first signal exceeds the voltage of the reference voltage source (15), on the other hand, the switch circuit (12) switches to a current source (7) so that the inputted differential signal is amplified and outputted only through the first differential couple (4).

Abstract: In a differential amplifier and an operational amplifier each for amplifying a signal, a differential signal composed of first and second signals is inputted to a couple of input terminals (1, 2). When the voltage of the first signal is, e.g., less than the voltage value of a reference voltage source (15), a comparator (13) senses it and a switch circuit (12) switches to a first current source (6) and a current from a third current source (11) flows into the first current source (6) so that a current is inhibited from flowing in the first differential couple (4). As a result, the inputted differential signal is amplified and outputted only through a second differential couple (5). In a situation in which the voltage of the first signal exceeds the voltage of the reference voltage source (15), on the other hand, the switch circuit (12) switches to a current source (7) so that the inputted differential signal is amplified and outputted only through the first differential couple (4).

Abstract: The receiver IF system or the signal selection device of the present invention includes: frequency converters that obtain polyphase intermediate-frequency signals for suppressing an image component of an RF signal from an input signal; a polyphase filter for removing an image component from the polyphase intermediate-frequency signals; and a band-pass filter composed of an N-pass filter for selecting a channel of an intermediate-frequency signal that is obtained by removing an image component from an output of the polyphase filter. An image rejection filter and a channel selection filter can be integrated at low cost with higher performance, and an area of a substrate for reception can be reduced.

Abstract: Four input nodes I1-I4 for inputting 4-phase signals, four resistors R1-R4, four capacitors C1-C4, and four output nodes O1-O4 for outputting 4-phase signals are provided. The resistors and the capacitors are connected alternately in a loop, and the input nodes and output nodes are connected alternately to the respective nodes between the resistors and the capacitors sequentially. Each of the four resistors is composed of a group of three or more partial resistors, and three groups of the partial resistors R2a-R2c, R3a-R3c and R4a-R4c are collected respectively and arranged in the same attitude, while the partial resistors R1a-R1c of the remaining group are distributed into the other groups and arranged in the same line the same attitude as the partial resistors of each of the other groups. The regions of the thus collected groups are arranged in one direction.

Abstract: In a differential amplifier and an operational amplifier each for amplifying a signal, a differential signal composed of first and second signals is inputted to a couple of input terminals (1, 2). When the voltage of the first signal is, e.g., less than the voltage value of a reference voltage source (15), a comparator (13) senses it and a switch circuit (12) switches to a first current source (6) and a current from a third current source (11) flows into the first current source (6) so that a current is inhibited from flowing in the first differential couple (4). As a result, the inputted differential signal is amplified and outputted only through a second differential couple (5). In a situation in which the voltage of the first signal exceeds the voltage of the reference voltage source (15), on the other hand, the switch circuit (12) switches to a current source (7) so that the inputted differential signal is amplified and outputted only through the first differential couple (4).

Abstract: A first second- or higher-order delta sigma modulator and a second second- or higher-order delta sigma modulator having a notch characteristic are cascaded together, and a delayed signal of the output of the first delta sigma modulator and a differential signal of the output of the second delta sigma modulator are added together. The amount of feedback from the output portion to the input portion of the first delta sigma modulator and the amount of feedback from the output portion to the input portion of the second delta sigma modulator are made the same.

Abstract: A receiver IF circuit includes the following: a variable gain amplifier for amplifying an RF input signal; a frequency converter for mixing the amplified RF input signal and a local signal to generate polyphase intermediate-frequency signals that are used for suppressing an image component; a polyphase filter for receiving the polyphase intermediate-frequency signals and outputting an intermediate-frequency signal whose image component is suppressed; a frequency variable band-pass filter for selecting a channel of the intermediate-frequency signal while changing a frequency response in accordance with a supplied control signal; an IF demodulator for demodulating the intermediate-frequency signal; and an automatic gain control for detecting a level of an output signal of the IF demodulator and controlling a gain of the variable gain amplifier in accordance with the detected level.

Abstract: A delta-sigma modulation quantization loop, comprising an integration circuit for integrating the difference between an analog input signal and a feedback reference voltage, a local quantizer for quantizing the output of the integration circuit into a digital signal, and a DA converter for generating the feedback reference voltage from the digital output of the local quantizer, is used as a single stage, and a plurality of the stages are cascade-connected. In the second-stage and subsequent modulation quantization loops, the difference signal between the input of the local quantizer of the previous stage and the output of the DA converter of the previous stage is used as an analog input signal. The feedback reference voltages of the respective delta-sigma modulation quantization loops are set individually so as to be higher than the specified maximum voltage of the analog input signal to limit the gains of the respective delta-sigma modulation quantization loops.