Patents by Inventor Akira Arahata

Akira Arahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769777
    Abstract: The present technology relates to a circuit board, a semiconductor device, and an electronic apparatus that reduce the generation of noise signals. A circuit board includes: a first conductor layer that has a first conductor portion including a conductor having a planar or mesh-like first basic pattern repeatedly disposed in the same plane; and a second conductor layer that has a second conductor portion including a conductor having a planar or mesh-like second basic pattern repeatedly disposed in the same plane, and a third conductor portion including a conductor having a planar, linear, or mesh-shaped third basic pattern repeatedly disposed in the same plane. The repeating cycles of the first and second basic patterns are substantially the same cycles, and the third basic pattern is different than the second basic pattern. The present technology can be applied to a circuit board of a semiconductor device and the like, for example.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 26, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takashi Miyamoto, Yoshiyuki Akiyama, Junichi Tsunoda, Shuuichi Kojima, Akira Arahata
  • Publication number: 20210126036
    Abstract: The present technology relates to a circuit board, a semiconductor device, and an electronic device that can more effectively curb occurrence of noise in a signal.
    Type: Application
    Filed: June 11, 2019
    Publication date: April 29, 2021
    Inventors: AKIRA ARAHATA, TAKASHI MIYAMOTO
  • Publication number: 20210036041
    Abstract: The present technology relates to a circuit board, a semiconductor device, and an electronic apparatus that reduce the generation of noise signals. A circuit board includes: a first conductor layer that has a first conductor portion including a conductor having a planar or mesh-like first basic pattern repeatedly disposed in the same plane; and a second conductor layer that has a second conductor portion including a conductor having a planar or mesh-like second basic pattern repeatedly disposed in the same plane, and a third conductor portion including a conductor having a planar, linear, or mesh-shaped third basic pattern repeatedly disposed in the same plane. The repeating cycles of the first and second basic patterns are substantially the same cycles, and the third basic pattern is different than the second basic pattern. The present technology can be applied to a circuit board of a semiconductor device and the like, for example.
    Type: Application
    Filed: March 8, 2019
    Publication date: February 4, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takashi MIYAMOTO, Yoshiyuki AKIYAMA, Junichi TSUNODA, Shuuichi KOJIMA, Akira ARAHATA
  • Patent number: 9060423
    Abstract: A laminated wiring board includes a plurality of wiring layers that are stacked with the intermediary of an insulating layer between the layers and have a four-layer wiring unit obtained by disposing a power supply layer, a ground layer, a first signal wiring layer, and a second signal wiring layer sequentially from one side to the other side of a layer stacking direction with the intermediary of an insulating layer between the layers. One of the first signal wiring layer and the second signal wiring layer includes a data signal line and the other includes a clock signal line. The data signal line and the clock signal line are so disposed as to be prevented from overlapping with each other in a view perpendicular to the layer stacking direction at least at a place where both lines are disposed as parallel lines.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: June 16, 2015
    Assignee: Sony Corporation
    Inventors: Satoshi Mizuno, Masafumi Oyama, Akira Arahata
  • Publication number: 20120201087
    Abstract: A laminated wiring board includes a plurality of wiring layers that are stacked with the intermediary of an insulating layer between the layers and have a four-layer wiring unit obtained by disposing a power supply layer, a ground layer, a first signal wiring layer, and a second signal wiring layer sequentially from one side to the other side of a layer stacking direction with the intermediary of an insulating layer between the layers. One of the first signal wiring layer and the second signal wiring layer includes a data signal line and the other includes a clock signal line. The data signal line and the clock signal line are so disposed as to be prevented from overlapping with each other in a view perpendicular to the layer stacking direction at least at a place where both lines are disposed as parallel lines.
    Type: Application
    Filed: January 13, 2012
    Publication date: August 9, 2012
    Applicant: Sony Corporation
    Inventors: Satoshi Mizuno, Masafumi Oyama, Akira Arahata