Abstract: An interconnection network is provided with switch devices for computers for a plurality of computers, respectively, a predetermined number of physical lines for switch devices for computers are bound to form each of logical lines, the physical lines forming the logical lines interconnect the other switch devices for computer via a plurality of switch devices for relay to form a parallel computer system. When a data transmission speed required between the computers is judged to be lower than a line transmission speed determined by the number of physical lines of any switch device for relay, switch setting-off unit turns off power of the whole switch device for relay that has been judged to shut off the switch device for relay from the interconnection network.

Abstract: A network management apparatus interconnects a plurality of computers through physical lines having a predetermined line speed to manage a switch apparatus constructing a parallel computer system. The switch apparatus comprises a plurality of physical port units to enable or disable the same through individual power supply ON/OFF control for the physical port units, thereby changing and controlling the line transmission speed according to the enable number. A logical port constructing unit in the network management apparatus bundles the physical lines by a plurality of physical port units in the switch apparatus to construct logical lines. A port control unit changes the number of operations of a plurality of physical port units assigned to the logical port units through the power supply ON/OFF control according to a necessary data transmission speed for the logical port units, thereby dynamically changing the line transmission speed.

Abstract: An interconnection network is provided with switch devices for computers for a plurality of computers, respectively, a predetermined number of physical lines for switch devices for computers are bound to form each of logical lines, the physical lines forming the logical lines interconnect the other switch devices for computer via a plurality of switch devices for relay to form a parallel computer system. When a data transmission speed required between the computers is judged to be lower than a line transmission speed determined by the number of physical lines of any switch device for relay, switch setting-off unit turns off power of the whole switch device for relay that has been judged to shut off the switch device for relay from the interconnection network.

Abstract: A network management apparatus interconnects a plurality of computers through physical lines having a predetermined line speed to manage a switch apparatus constructing a parallel computer system. The switch apparatus comprises a plurality of physical port units to enable or disable the same through individual power supply ON/OFF control for the physical port units, thereby changing and controlling the line transmission speed according to the enable number. A logical port constructing unit in the network management apparatus bundles the physical lines by a plurality of physical port units in the switch apparatus to construct logical lines. A port control unit changes the number of operations of a plurality of physical port units assigned to the logical port units through the power supply ON/OFF control according to a necessary data transmission speed for the logical port units, thereby dynamically changing the line transmission speed.

Abstract: A data processing device includes an instruction storage memory which stores load instructions by eliminating NOP instructions for insertion into a load module of a VLIW computer. The data processing device also includes a device to expand the compressed load module automatically by a hardware circuit during instruction execution. The data processing device compresses and stores specific instruction code strings in memory with information indicating a form of compression and then restores the instruction code strings to an original format when read from memory according to the compression information. Information indicating an original storage position is attached to each instruction code, instruction code strings are stored in memory without specific instruction codes, and then restored to the original code strings when read from memory according to the storage position information.

Abstract: A data processing system which is able to execute, decode and encode process variable length code (VLC) data in a finite number of programming steps and thereby reduce the time required to manipulate VLC data. This is accomplished by using buffer registers to store VLC data loaded from memory and VLC data to be stored to memory. Offset registers are used to indicate the size of the blank region within the buffer registers provided. Using these offset registers load and store processing between the memory and buffer registers and shift processing within the buffer registers can easily be accomplished.

Abstract: A data processing device having a pipeline bypass function passes an operation result of a preceding instruction to a succeeding instruction as a source operand before writing the operation result to a register. A source operand bypass specification field and a source operand register field in the instruction code are provided to control passing of the operation result. A source operand selector responds to the source operand bypass specification field by selecting data either from the register or the bypasses as a pipeline input data.

Abstract: A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each slot of the VLIW instruction, is divided corresponding to each slot and stored into a plurality of intermediate code files. The instructions of the intermediate code format stored in the intermediate code files are then read in serially to execute an instruction scheduling process, taking into account dependency between instructions. The serialized instructions of the intermediate code format are converted into parallel assembly code, and an object program of the parallel assembly code is output.