Patents by Inventor Akira Bandoh
Akira Bandoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190316273Abstract: A method of producing a p-type SiC epitaxial wafer, the method including: a step of setting an input raw material C/Si ratio, being a ratio between the C element and the Si element in a feedstock gas; and a step of obtaining a p-type SiC epitaxial wafer having an Al dopant concentration of at least 1×1018 cm?3 by forming a p-type SiC epitaxial film on a substrate in a film-forming atmosphere comprising the feedstock gas, a Cl-based gas containing Cl in the molecule, and a dopant gas containing Al and C in the molecule, wherein the input raw material C/Si ratio is set based on a total gas C/Si ratio, being a ratio between the C element and the Si element in the film-forming atmosphere containing the C element included in the dopant gas, the input raw material C/Si ratio differs from the total gas C/Si ratio, and the input raw material C/Si ratio is 0.8 or less.Type: ApplicationFiled: December 11, 2017Publication date: October 17, 2019Applicant: SHOWA DENKO K.K.Inventors: Naoto ISHIBASHI, Keisuke FUKADA, Akira BANDOH
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Patent number: 9064696Abstract: Provided is an apparatus for manufacturing a compound semiconductor, which forms a compound semiconductor layer using a metal-organic chemical vapor deposition method. The apparatus is characterized in that: the apparatus is provided with a reaction container, a holder, which is disposed in the reaction container and has placed thereon a subject, on which the layer is to be formed, the subject having facing up the subject surface where the layer is to be formed, and a raw material supply port, through which the raw material gas of the compound semiconductor is supplied to the inside of the reaction container from the outside; the holder is in contact with the lower surface of the subject, the contact being inside of the outer circumferential portion of the subject to the center of the upper surface of the holder; and that the holder has a supporting portion, which supports the subject such that a predetermined interval is maintained between the upper surface of the holder and the lower surface of the subject.Type: GrantFiled: August 16, 2011Date of Patent: June 23, 2015Assignee: TOYODA GOSEI CO., LTD.Inventors: Hideki Yasuhara, Akira Bandoh
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Patent number: 8753448Abstract: Provided is an apparatus for manufacturing a compound semiconductor by use of metal organic chemical vapor deposition including: a reaction container; a holder on which a formed body is to be placed so that a formed surface of the formed body on which layers of a compound semiconductor are to be formed faces upward, the holder being arranged in the reaction container; and a material supply port supplying a material gas of the compound semiconductor into the reaction container from outside, wherein the holder includes a support member supporting the formed body so that an undersurface of the formed body and a top surface of the holder on which the formed body is to be placed keep a predetermined distance.Type: GrantFiled: February 23, 2012Date of Patent: June 17, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Hideki Yasuhara, Akira Bandoh
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Publication number: 20130143393Abstract: Provided is an apparatus for manufacturing a compound semiconductor, which forms a compound semiconductor layer using a metal-organic chemical vapor deposition method. The apparatus is characterized in that: the apparatus is provided with a reaction container, a holder, which is disposed in the reaction container and has placed thereon a subject, on which the layer is to be formed, the subject having facing up the subject surface where the layer is to be formed, and a raw material supply port, through which the raw material gas of the compound semiconductor is supplied to the inside of the reaction container from the outside; the holder is in contact with the lower surface of the subject, the contact being inside of the outer circumferential portion of the subject to the center of the upper surface of the holder; and that the holder has a supporting portion, which supports the subject such that a predetermined interval is maintained between the upper surface of the holder and the lower surface of the subject.Type: ApplicationFiled: August 16, 2011Publication date: June 6, 2013Applicant: TOYODA GOSEI CO., LTD.Inventors: Hideki Yasuhara, Akira Bandoh
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Publication number: 20120146191Abstract: Provided is an apparatus for manufacturing a compound semiconductor by use of metal organic chemical vapor deposition including: a reaction container; a holder on which a formed body is to be placed so that a formed surface of the formed body on which layers of a compound semiconductor are to be formed faces upward, the holder being arranged in the reaction container; and a material supply port supplying a material gas of the compound semiconductor into the reaction container from outside, wherein the holder includes a support member supporting the formed body so that an undersurface of the formed body and a top surface of the holder on which the formed body is to be placed keep a predetermined distance.Type: ApplicationFiled: February 23, 2012Publication date: June 14, 2012Applicant: SHOWA DENKO K.K.Inventors: Hideki YASUHARA, Akira BANDOH
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Patent number: 7855386Abstract: An object of the present invention is to provide a low-resistance n-type Group III nitride semiconductor layered structure having excellent flatness and few pits. The inventive n-type group III nitride semiconductor layered structure comprises a substrate and, stacked on the substrate, an n-type impurity concentration periodic variation layer comprising an n-type impurity atom higher concentration layer and an n-type impurity atom lower concentration layer, said lower concentration layer being stacked on said higher concentration layer.Type: GrantFiled: April 27, 2005Date of Patent: December 21, 2010Assignee: Showa Denko K.K.Inventors: Akira Bandoh, Hiromitsu Sakai, Masato Kobayakawa, Mineo Okuyama, Hideki Tomozawa, Hisayuki Miki, Joseph Gaze, Syunji Horikawa, Tetsuo Sakurai
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Patent number: 7646027Abstract: An object of the present invention is to provide a Group III nitride semiconductor stacked structure with a low dislocation density obtained by stacking only a semiconductor layer on a flat substrate by the use of a normal epitaxial growth method without processing the substrate or a deposit layer on the substrate, wherein the dislocation density is 1×107 cm?2 or less. The inventive Group III nitride semiconductor stacked structure comprises a substrate having a surface roughness (Ra) of 1 nm or less and a Group III nitride semiconductor layer directly stacked on the substrate, wherein the Group III nitride semiconductor layer comprises a plurality of layers put into contact with each other, the plurality of layers comprise a high-concentration impurity atom layer and a low-concentration impurity atom layer, and the high-concentration impurity atom layer is present on the substrate side.Type: GrantFiled: May 3, 2006Date of Patent: January 12, 2010Assignee: Showa Denko K.K.Inventor: Akira Bandoh
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Publication number: 20080230800Abstract: An object of the present invention is to provide a low-resistance n-type Group III nitride semiconductor layered structure having excellent flatness and few pits. The inventive n-type group III nitride semiconductor layered structure comprises a substrate and, stacked on the substrate, an n-type impurity concentration periodic variation layer comprising an n-type impurity atom higher concentration layer and an n-type impurity atom lower concentration layer, said lower concentration layer being stacked on said higher concentration layer.Type: ApplicationFiled: April 27, 2005Publication date: September 25, 2008Inventors: Akira Bandoh, Hiromitsu Sakai, Masato Kobayakawa, Mineo Okuyama, Hideki Tomozawa, Hisayuki Miki, Joseph Gaze, Syunji Horikawa, Tetsuo Sakurai
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Publication number: 20070241352Abstract: It is an object of the present invention to provide a simple and reliable method for forming a rough structure having inclined side surfaces in a light emitting device, and to provide a group III nitride semiconductor light emitting device that is obtained by the method and is excellent in light extraction efficiency. The inventive group III nitride semiconductor light emitting device comprising group III nitride semiconductor formed on a substrate comprises a first layer of Ge doped group III nitride semiconductor having pits on the surface thereof, and a second layer adjoining on the first layer and having a refractive index different from that of the first layer.Type: ApplicationFiled: June 16, 2005Publication date: October 18, 2007Applicant: Showa Denko K. K.Inventors: Takaki Yasuda, Akira Bandoh
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Publication number: 20060261353Abstract: An object of the present invention is to provide a Group III nitride semiconductor stacked structure with a low dislocation density obtained by stacking only a semiconductor layer on a flat substrate by the use of a normal epitaxial growth method without processing the substrate or a deposit layer on the substrate, wherein the dislocation density is 1×107 cm?2 or less. The inventive Group III nitride semiconductor stacked structure comprises a substrate having a surface roughness (Ra) of 1 nm or less and a Group III nitride semiconductor layer directly stacked on the substrate, wherein the Group III nitride semiconductor layer comprises a plurality of layers put into contact with each other, the plurality of layers comprise a high-concentration impurity atom layer and a low-concentration impurity atom layer, and the high-concentration impurity atom layer is present on the substrate side.Type: ApplicationFiled: May 3, 2006Publication date: November 23, 2006Inventor: Akira Bandoh