Abstract: A cache memory control system has a segment descriptor with a 1-bit cache memory unit designation field, and a register for storing data representing the cache memory unit designation field. An output from the register is supplied to one cache memory unit, whereas inverted data of the output from the register is supplied to the other cache memory unit.

Abstract: A data processing system which include a central processing unit having a program counter, a main memory for storing a return instruction including the contents of the program counter and interrupting inhibiting information and for storing the contents of a general register in the CPU, interruption means for controlling the storage of the return instruction and the general register contents in the main memory upon occurrence of a first interruption, detection means for reading the return instruction stored in the main memory upon completion of the first interruption and for initiating the immediate occurrence of a second interruption in accordance with the inhibiting information of the return instruction read in the main memory, and return means for restoring the return instruction and the general register contents stored in the main memory to the central processing unit in the event that the detecting means determines that there is no further interruption to be accepted.