Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system including a switch unit having a plurality of input ports and output ports, and a multiplexer for multiplexing cell trains from at least two output ports into a single cell train and outputting the cell train to and output port. A demultiplexer can be provided in place of the multiplexer. The switch unit includes a buffer memory for storing cells from the input ports while forming a queue chain for each output port, a demultiplexer for distributing the cells from the buffer memory to output ports, and a buffer memory control circuit for controlling write and read operations of the buffer memory. The buffer memory control circuit has a control table for outputting an identifier of an output port the cells read from the buffer memory are to be output. Cells are read from the chain designated by the identifier.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: In a system comprising input/output devices, a memory and a control processor, direct memory access information (memory address and data) from an input/output device to the processor is stored temporarily and then a direct memory access request is transmitted to the processor. The processor bus holding time at direct memory access is reduced, and the processing speed of the processor is improved.

Abstract: A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.

Abstract: In order to enable an expansion of a packet switched network and a constitution change thereof to be readily achieved in a multistage switched network constitution, in a packet switched network including a packet data terminal, a packet switching equipment, a PBX, a multiplexer, an LAN, a voice communication apparatus such as a telephone set, and a facsimile or in a linkage between switching modules in a packet switching apparatus, the basic switching modules called configuration units connected to the network are interconnected to each other to form a hierarchic tree structure of which the number of hierarchic levels can be selected depending on a size of the packet switched network. Furthermore, in order to increase the reliability of the packet data transfer in the multi-stage switched network configuration, there are disposed a plurality of connecting lines between bit switches and upper-level configuration units so as to establish a redundant configuration.

Abstract: In a composite concentration system of the type utilizing a time division system in which voice signals are digitized and then concentrated in a traffic, there are provided a first subscriber line interface means of a first type which connects subscriber lines directly to subscriber line interface circuits, a second subscriber line interface means of a second type which connects subscriber lines to subscriber line interface circuits via a space division concentration switch and a time division concentration switch connected to the first and second subscriber line interface means via switching interfaces.

Abstract: A voice signal converting device is adapted for a digital communication network which handles digitized voice signals and data signals simultaneously or equally. A bit for discriminating whether a signal in communication is a voice signal or a data signal is applied in a digital signal channel. The voice signal converting device is connected to a digital communication path to detect the discrimination bit from the incoming signal in such a manner that when a bit group corresponding to the discrimination bit represents the voice signal, the bit group is converted into a predeterminedly correlated bit group and delivered out and when the bit group corresponding to the discrimination bit represents the data signal, this bit group is delivered out in its original form.

Abstract: A supervisory and control system for a time division switching system supervising and controlling signals transferring to and from all or some of line interface equipment such as a digital trunk, analog trunk equipment, the intra-office line concentrators or remote line concentrator through a signal path. In the signal control, the signal is classified into two kinds of signals: one for cyclically controlling a state and the other for randomly controlling the same. Those signals are multiplexed in a single time slot to control the various line interfaces. Signal time slots having different multiframes and signal time slots with a plurality of periods are supervised depending on a signal path class thereby to reduce the number of laying cables among interframes.

Abstract: An immediate ring-back control system in a time-division telephone exchange comprising a time-division switching network of an incoming time switch-space switch-outgoing time switch (T-S-T) system. A continuous ring-back tone is supplied to a plurality of successive addresses of the incoming time switch and an interrupted ring-back tone is supplied to at least one address thereof. Upon connection of the ring-back tone, a first address number of the successive addresses supplied with the continuous ring-back tone is written into a control memory corresponding to the time switch while the successive addresses are sequentially increased for each count of a timing pulse generated periodically. The content of the control memory is modified by the address number successively increased and the successive address numbers are modified to the address number to which the interrupted ring-back tone is supplied, thereby to reduce a post dialling delay.

Abstract: An immediate ring-back control system for a time-division telephone exchange includes a time-division switching network of a time switch-space switch-time switch (T-S-T) system. An incoming time switch accommodates multi-channel interrupted ring-back tones (IRBT's) which are generated by a tone generator in a time-multiplexed manner, each of which has a different interruption phase. The interrupted ring-back tone having a phase starting from a tone-sending period is selected from the multi-channel interrupted ring-back tones (IRBT's) by an immediate ring-back control circuit provided in a time-division switch driving circuit (SDC) at the time of connection of the ring-back tone to a calling subscriber, and a channel number corresponding to the phase of the interrupted ring-back tone is stored in a control memory or a time slot memory associated with the time switch, so that the transmission of the interrupted ring-back tones to a calling subscriber can be started from a mark portion thereof.

Abstract: An analog-digital code converter in a digital telephone switching system is disclosed wherein when an analog voice signal from an analog line is applied to an analog per line unit it is sampled at a high rate and a high speed sampling digital code produced by .DELTA.M-PCM modulation is converted to a low speed sampling digital code through a digital filter provided in a common unit for application to a time division digital speech path switch, and when a wide band broadcasting service signal from the same analog line is applied to the analog per line unit, a path is provided between the analog per line unit and the time division digital speech path switch which path bypasses the digital filter without allowing the conversion of the high speed sampling digital code of the analog per line unit to the low speed sampling digital code, whereby wide band communication as well as ordinary speech band communication are attained.

Abstract: A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.