Abstract: A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of the corresponding transistor are connected together by an intermediate interconnection line extending only in the region having the corresponding address interconnection line arranged. Accordingly, a high speed switching of address signals can be achieved.

Abstract: An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.

Abstract: An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.

Abstract: A semiconductor memory device operating in synchronization with an external clock signal, includes memory cells arrayed in two dimension, word lines and bit lines connected to the memory cells, IO lines connected to the bit lines, and a sense amplifier connected to the IO lines and activated by a sense amplifier enable signal. After the word line is selected, an internal clock signal is generated by delaying the rising and falling edges of the external clock signal input to the memory device. A timing at which the internal clock signal changes from a first state to a second state is delayed by a predetermined time to make the sense amplifier enable signal active, and a timing at which the internal clock signal changes from the second state to the first state is delayed by a shorter period than the predetermined time to make the sense amplifier enable signal inactive.

Abstract: A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of the corresponding transistor are connected together by an intermediate interconnection line extending only in the region having the corresponding address interconnection line arranged. Accordingly, a high speed switching of address signals can be achieved.

Abstract: When a stage increasing signal, which is input into a sub boosting circuit, is at the L level, three boosting stages are used within the sub boosting circuit to boost a supply potential. On the other hand, when the stage increasing signal is at an H level, four boosting stages are used within the sub boosting circuit to boost the supply potential. Thus, by the semiconductor integrated circuit device of the invention, an internal potential can be boosted at a high speed while power consumption can be reduced.

Abstract: A specific row of memory cells in a flash memory is set to be in a lock mode state, which affects reading of data in other rows of memory cells in a common memory array. Thus, a flash memory having a data concealing function is achieved.

Abstract: In a chip with pads provided on four sides, I/O defects of the chip can be determined with test probes applied to two sides of the chip. A semiconductor storage unit has data pads which input/output data arranged on predetermined two sides, and control pads which input/output control data arranged on other two sides. The unit includes test circuits connected in series and connected to a corresponding data pads and has a register circuit. The register circuit holds and outputs inputted data based on a test signal. Storage elements stores data and are connected to a corresponding test circuit. At the time of testing, the elements store the data from a predetermined data pad and transmitted to a predetermined test circuit. The register circuit reads the data in the corresponding storage element and outputs the data from the predetermined data pad via other register circuit.

Abstract: Transistors are provided on both sides of sense latches. When a good sector code “10101100” is latched by sense latches, a current sense amplifier detects that common drain lines are non-conductive, thereby determining whether a good sector code is written in each sector or not. As a result, this flash memory can determine whether each of sectors is good or not without outputting a good sector code from the flash memory in which a good sector code is written in a good sector.

Abstract: An internal voltage from an internal voltage generating circuit is transmitted to a pad in accordance with a control signal, and a buffer circuit coupled to the pad is set in an inactive state. The pad is connected to an external pin terminal via a bonding wire. Consequently, a semiconductor integrated circuit capable of monitoring and forcedly setting an internal voltage from an outside of the circuit device is realized with a minimum number of pin terminals without increasing the number of external pin terminals.

Abstract: When a stage increasing signal, which is input into a sub boosting circuit, is at the L level, three boosting stages are used within the sub boosting circuit to boost a supply potential. On the other hand, when the stage increasing signal is at an H level, four boosting stages are used within the sub boosting circuit to boost the supply potential. Thus, by the semiconductor integrated circuit device of the invention, an internal potential can be boosted at a high speed while power consumption can be reduced.

Abstract: A specific row of memory cells in a flash memory is set to be in a lock mode state, which affects reading of data in other rows of memory cells in a common memory array. Thus, a flash memory having a data concealing function is achieved.

Abstract: In a data register latching a data on a selected memory cell of a memory array, circuitry is provided for repairing a defect when the defect is present in a latch circuit included in the data register. The defect repairing is implemented by reverse current flow prevention for a latch power supply, of a determination transistor into a non-conductive state, determination with a forcibly setting circuit, inversion of a latch data, switching of current detectors. A product yield is improved by repairing the defect even when the defect is present in a latch circuit section in which a data is latched.

Abstract: An internal voltage from an internal voltage generating circuit is transmitted to a pad in accordance with a control signal, and a buffer circuit coupled to the pad is set in an inactive state. The pad is connected to an external pin terminal via a bonding wire. Consequently, a semiconductor integrated circuit capable of monitoring and forcedly setting an internal voltage from an outside of the circuit device is realized with a minimum number of pin terminals without increasing the number of external pin terminals.

Abstract: A data latch circuit group latches data read by a sense latch circuit group when a read voltage is supplied to a word line. These data are transferred to a read data conversion circuit and converted to 2-bit data. Thus, no operation processing may be performed through a bit line or a transistor in a memory cell array, whereby a read time can be reduced for reducing power consumption.

Abstract: In response to complementary clock signals provided from a driver, a charge pump operates to provide an output voltage which is a down-converted negative voltage. The voltage between this output voltage and a predetermined positive reference voltage is capacitance-divided by capacitors. The capacitance-divided positive voltage is applied to a comparator, whereby a reference voltage is compared with the above positive voltage. An output signal of the comparator is applied to the driver. In response, the driver controls the operation of the charge pump, whereby the output voltage is clamped at a predetermined voltage level for output.

Abstract: A bit line reset transistor resets every second bit line of a plurality of bit lines to be write-verified. At this time, a transfer gate disconnects a column latch from the unreset bit line. Then, the unreset bit line is precharged in accordance with data of the column latch, while applying a verify voltage to a word line. Then, a source line transistor grounds a source line, and the bit line is connected to the column latch, so that data corresponding to a value of a threshold voltage of the memory cell is held by the column latch, and a write verifying operation is performed.

Abstract: A level converting circuit has a function of converting an input signal of a first logic level into an output signal of a second logic level. The level converting circuit includes a first transistor responsive to an input signal IN for charging an output node to the ground potential, a second transistor responsive to the input signal IN for lowering the potential of the output node to the negative potential VEE, a third transistor responsive to the potential of the output node for controlling operations of the second transistor, and fourth and fifth transistors responsive to a delay signal with delay to an output of the level converting circuit for controlling the amount of current flowing through the output node. An inverted, amplified signal of the output node is applied to the gate of the fourth transistor, and a non-inverted, amplified signal of the output node is applied to the gate of the fifth transistor.