Patents by Inventor Akira Hyogo

Akira Hyogo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160329881
    Abstract: An amplifying circuit according to an embodiment includes a sample and hold circuit, an operational amplifier, a feedback capacitance, and a level shift circuit. The sample and hold circuit includes a sampling capacitance to sample an analog input signal in a sampling phase. The operational amplifier amplifies and outputs the analog input signal held by the sampling capacitance in the amplifying phase. The feedback capacitance is connected between the input terminal of the operational amplifier and the analog output terminal. The level shift circuit includes a level shift capacitance to sample the analog input signal in the sampling phase. A plurality of level shift capacitances is provided and connected in cascade between the output terminal of the operational amplifier and the analog output terminal.
    Type: Application
    Filed: March 4, 2016
    Publication date: November 10, 2016
    Applicants: KABUSHIKI KAISHA TOSHIBA, Tokyo University of Science Foundation
    Inventors: Junya MATSUNO, Masanori FURUTA, Tetsuro ITAKURA, Akira HYOGO, Tatsuji MATSUURA, Takuya HARA
  • Publication number: 20100201447
    Abstract: A radio-frequency circuit comprises a low-noise amplifier, an NMOS mixer for converting a radio-frequency signal output from the low-noise amplifier into an intermediate-frequency signal, a polyphase filter for removing image noises, and a PMOS mixer for converting the intermediate-frequency signal passed through the polyphase filter into a baseband signal.
    Type: Application
    Filed: April 21, 2010
    Publication date: August 12, 2010
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADAMIC RESEARCH CENTER
    Inventors: Akira Hyogo, Satoshi Tanaka, Tetsuro Sawai, Kenichi Agawa, Hirotada Honma, Ryutaro Saito, Tomoki Hikichi, Keitaro Sekine
  • Patent number: 7171178
    Abstract: A tuning circuit having an amplitude-varying function is disclosed that comprises a coil, a capacitor, and a resistance-adjusting element connected in parallel to the coil and the capacitor for varying resistance at time of resonance of the tuning circuit, wherein the amplitude of an output signal of the tuning circuit is varied by varying the resistance with the resistance-adjusting element.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: January 30, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masahiro Umewaka, Hiroya Yamamoto, Keitaro Sekine, Akira Hyogo, Keiji Morijiri
  • Publication number: 20060194559
    Abstract: A radio-frequency circuit comprises a low-noise amplifier, an NMOS mixer for converting a radio-frequency signal output from the low-noise amplifier into an intermediate-frequency signal, a polyphase filter for removing image noises, and a PMOS mixer for converting the intermediate-frequency signal passed through the polyphase filter into a baseband signal.
    Type: Application
    Filed: February 15, 2006
    Publication date: August 31, 2006
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Akira Hyogo, Satoshi Tanaka, Tetsuro Sawai, Kenichi Agawa, Hirotada Honma, Ryutaro Saito, Tomoki Hikichi, Keitaro Sekine
  • Publication number: 20040198285
    Abstract: A tuning circuit having an amplitude-varying function is disclosed that comprises a coil, a capacitor, and a resistance-adjusting element connected in parallel to the coil and the capacitor for varying resistance at time of resonance of the tuning circuit, wherein the amplitude of an output signal of the tuning circuit is varied by varying the resistance with the resistance-adjusting element.
    Type: Application
    Filed: January 23, 2004
    Publication date: October 7, 2004
    Inventors: Masahiro Umewaka, Hiroya Yamamoto, Keitaro Sekine, Akira Hyogo, Keiji Morijiri
  • Patent number: 6791413
    Abstract: A variable gain amplifier is configured of an amplification circuit and a control circuit controlling a gain of the amplification circuit. The amplification circuit has first and second MOS transistors identical in characteristics and having respective sources connected to a first fixed potential. The amplification circuit has a differential gain proportional to a square root of a ratio between a current flowing through the first MOS transistor and a current flowing through the second MOS transistor. The control circuit applies a potential corresponding to a constant voltage plus a control voltage to a gate of the first MOS transistor and a potential corresponding to the constant voltage minus the control voltage to a gate of the second MOS transistor.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Komurasaki, Hisayasu Satoh, Kinya Hosoda, Akira Hyogo, Keitaro Sekine
  • Publication number: 20040046608
    Abstract: A variable gain amplifier is configured of an amplification circuit and a control circuit controlling a gain of the amplification circuit. The amplification circuit has first and second MOS transistors identical in characteristics and having respective sources connected to a first fixed potential. The amplification circuit has a differential gain proportional to a square root of a ratio between a current flowing through the first MOS transistor and a current flowing through the second MOS transistor. The control circuit applies a potential corresponding to a constant voltage plus a control voltage to a gate of the first MOS transistor and a potential corresponding to the constant voltage minus the control voltage to a gate of the second MOS transistor.
    Type: Application
    Filed: March 10, 2003
    Publication date: March 11, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroshi Komurasaki, Hisayasu Satoh, Kinya Hosoda, Akira Hyogo, Keitaro Sekine