Abstract: An imaging apparatus is provided that includes: a video input unit configured to take an image of an object to generate an image signal of the object; a video signal processor configured to generate a taken image of the object on a basis of the image signal; and a controller configured to: detect motion information of the object on the basis of the image signal; cause the video input unit to take an image of the object on a basis of the motion information multiple times so as to differentiate an exposure amount thereof; and cause the video signal processor to generate an HDR synthetic image of the object on the basis of a plurality of image signals whose exposure amounts are different from each other.

Abstract: For establishing cooperation among an external device 30, a video display device 10 and a remote control terminal 20 and to achieve cooperative operation among these devices that affords a high level of operability to a user with less burden, the video display device 10 to which an external device 30 and a remote control terminal 20 that remotely operates the external device can be connected, comprising: a connection detection section 140 configured to detect a connection of the external device 30 to the video display device 10; a cooperation establishment section 120 configured to generate a start signal for initiate an application software accepting an operation instruction to the external device 30 on the remote control terminal 20 when the connection detection section 140 detects the connection of the external device 30; and a communication interface 18 configured to transmit the start signal to the remote control terminal.

Abstract: The invention is characterized in that, when protrusion parts 30 are raised from a substrate W and the protrusion parts 30 are formed into spacers 12 with a predetermined outer diameter D and height H, the protrusion parts 30 are temporarily formed so as to have a diameter larger than a predetermined outer diameter D and a height larger than a predetermined height H, and the protrusion parts 30 are crushed, and leading end portions 30b of the protrusion parts 30 are protruded in a radially outward direction so as to have a double-layered structure, and then through-holes 35 are opened at the leading end portions 30b. Accordingly, the leading end portions 30b have strength due to a double-layered structure, and side portions 30a also have high strength due to contraction by pressing, whereby the sleeve-integrated member includes the entirely high-strength spacers 12.

Abstract: The invention is characterized in that, when protrusion parts 30 are raised from a substrate W and the protrusion parts 30 are formed into spacers 12 with a predetermined outer diameter D and height H, the protrusion parts 30 are temporarily formed so as to have a diameter larger than a predetermined outer diameter D and a height larger than a predetermined height H, and the protrusion parts 30 are crushed, and leading end portions 30b of the protrusion parts 30 are protruded in a radially outward direction so as to have a double-layered structure, and then through-holes 35 are opened at the leading end portions 30b. Accordingly, the leading end portions 30b have strength due to a double-layered structure, and side portions 30a also have high strength due to contraction by pressing, whereby the sleeve-integrated member includes the entirely high-strength spacers 12.

Abstract: A data processing system is provided which includes a plurality of subsystems each including at least one instruction processor, at least one input/output device and at least one main storage device connected by local bus. The subsystems are connected to one another through bus extenders and inter-subsystem transfer lines. Each of the main storage devices is assigned for a partial address space as a part of the system address space. When an instruction processor or an input/output processor on each of the subsystems makes access to a main storage device, the operation of the system is as follows. If the address of access is in the address space limit of a main storage device on an inner subsystem, access to the main storage device on the inner subsystem is made.

Abstract: A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.

Abstract: Provided is an information processing apparatus in which at least two processing units each having a buffer memory are mutually connected to each other and to a main storage unit through a bus. All of the processing units having the buffer memories continuously monitor the state of the bus. When one of the processing units generates an information updating request in order to update the storage content of the main storage unit, the other processing units read a memory address from the bus. The memory address corresponds to the information to be updated, and is sent to the main storage unit through the bus together with the information updating request. The memory address is compared with memory addresses contained in the buffer memory of the other processing units. If there is a coincidence, information in the relevant memory address exists in its own buffer memory. Thereafter this information is invalidated.

Abstract: A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.