Abstract: On an interface between LSIs, boards, devices (units), and others, the data transfer efficiency per signal line is improved. A shift circuit 710-0 shifts a piece of digital signal D1(0) for output as three digital signals D1S(00) to (02). An analog conversion circuit 720-0 converts the three digital signals D1S(00) to (02) into a piece of analog signal A2(0) for transfer. A digital conversion circuit 730-0 converts the piece of analog signal A2(0) into three digital signals D3(00) to (02). A selection circuit 740-0 makes a sequential selection from the three digital signals D3(00) to (02) to output a piece of digital signal D4(0).

Abstract: Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN1 to IN3 are supplied to diffusion layer regions 221, 223 and 225 via transistors 301 to 303, and are accumulated as electric charge. A clock signal is applied to signal lines 121 and 122 alternately connected to gate electrodes 211 to 216, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifiers 411 to 413 are connected to the diffusion layer regions 221, 223 and 225, and the accumulated electric charge is converted into voltage and is output to output terminals VOUT1 to VOUT3 as analog signals. A scan-in terminal Sin is connected to a diffusion layer region 220, and a scan-out terminal Sout is connected to the diffusion layer region 225 via an electric charge/voltage conversion amplifier 401.

Abstract: An antenna is realized by a simple mechanism without use of a dedicated antenna element. An antenna includes a first conductor 2b (2d) that has a first line length from a start point 4 to a folded point 3; and a second conductor 2b (2d) that has a second line length in a direction from the folded point 3 to the start point 4 and is electrically connected to the first conductor at the folded point 3. A first received signal with a first frequency is received with a first antenna length including both the first line length and the second line length. A second received signal with a second frequency is received with a second antenna length including only one of the first line length and the second line length.

Abstract: On an interface between LSIs, boards, devices (units), and others, the data transfer efficiency per signal line is improved. A shift circuit 710-0 shifts a piece of digital signal D1(0) for output as three digital signals D1S(00) to (02). An analog conversion circuit 720-0 converts the three digital signals D1S(00) to (02) into a piece of analog signal A2(0) for transfer. A digital conversion circuit 730-0 converts the piece of analog signal A2(0) into three digital signals D3(00) to (02). A selection circuit 740-0 makes a sequential selection from the three digital signals D3(00) to (02) to output a piece of digital signal D4(0).

Abstract: Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN1 to IN3 are supplied to diffusion layer regions 221, 223 and 225 via transistors 301 to 303, and are accumulated as electric charge. A clock signal is applied to signal lines 121 and 122 alternately connected to gate electrodes 211 to 216, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifiers 411 to 413 are connected to the diffusion layer regions 221, 223 and 225, and the accumulated electric charge is converted into voltage and is output to output terminals VOUT1 to VOUT3 as analog signals. A scan-in terminal Sin is connected to a diffusion layer region 220, and a scan-out terminal Sout is connected to the diffusion layer region 225 via an electric charge/voltage conversion amplifier 401.

Abstract: The present invention concerns a dustproof mechanism for a detecting means comprising comprises a detecting position, through which substances to be detected are passed at a prescribed position of a detecting optical path, which is formed on one side of the detecting position. The dustproof mechanism provides at least two air chambers between the detecting portion and the detecting position in a manner that these air chambers are perforated through the optical path to make open holes.

Abstract: An automatic high-speed pill counting apparatus comprising: a cylindrical pill hopper 3 having a pill exit 10 and a center hole in a base plate 2; a rotational separative feeder 5 mounted in the cylindrical pill hopper and removably fitted on a shaft 6 borne in the center hole of the base plate, the feeder including an upper diametrically smaller portion 5b and a lower diametrically larger portion 5c having an external diameter approximate to the internal diameter of the lower portion of the pill hopper, a multiplicity of vertically through holes 5c being formed in the outer circumference of the lower diametrically larger portion and allowed to come into alignment with the pill exit for accommodating a plurality of pills vertically, the multiple vertically through holes 5d being enlarged at their lower portions, a ring-shaped slit 8 being formed in such a position in the outer circumference of the lower diametrically larger portion as to accommodate substantially one pill from the bottom; and a pill separatin

Abstract: A pipeline circuit is capable of adjusting the timing of data, in a data processing system for ensuring processing, even if the input timings of different data are irregular or the input data are invalid. This is achieved by generating a selection signal, which is input to a data holding circuit. The selection signal determines the particular register in which a datum is stored. The value of the selection signal is determined by an input indicating signal, which indicates whether a particular datum is valid or invalid. When the data is valid the selection signal is shifted to the next value, indicating the next higher register, and when the data is invalid the selection signal maintains the value it had for the previous datum.

Abstract: A summing circuit (20) is for summing up zeroth through n-th input data signals A(0) to A(n) to produce a sum signal S consisting of zeroth through m-th output bits s(0) to s(m) where n represents a first predetermined natural number and m represents a second predetermined natural number which is not less than the first predetermined natural number. A preprocessing circuit (22) preprocesses the zeroth through the n-th input data signals A(0) to A(n) into a preprocessed signal which is (n+1) bits long. A logic circuit (24) carries out a logical operation on the preprocessed signal to produce the sum signal S. For example, each of the zeroth through the n-th input data signals A(0) to A(n) is given by an equation: ##EQU1## where a(d) represents a d-th coefficient having one of logic zero and one values, k represents a predetermined integer which is not less than zero, and A represents a common coefficient having the logic zero value.

Abstract: In an error detection circuit for use in combination with a logic unit to detect an error by monitoring a binary signal of k bits in a logic circuit which carries out a predetermined operation with respect to a modulus number, where m is equal to 2.sup.k -1, zeroth through (m-1)-th codes are assigned to the predetermined operation while an m-th code is prepared as a specific code to monitor and to detect an error in the error detection circuit. The logic circuit may be either one of a modulo-m register circuit, a modulo-m coincidence circuit, and a modulo-m calculation circuit. Alternatively, at least two of the modulo-m circuits may be combined to form the logic circuit. If m=3, the specific code may be (1, 1).

Abstract: In an operation for winding a synthetic thread on a cylindrical bobbin for producing a full size yarn package at a winding speed more than 2500 m/min, the possible creation of defective yarn winding is positively prevented by increasing the tightness of the winding thread on a just previously formed thread layer of the yarn package, at least once in a predetermined period defined by a critical condition. Such predetermined period is defined by1.20.times.10.sup.-6 .ltoreq. (dw/dt)/D .ltoreq. 3.0.10.sup. -6wherein w represents the number of bobbin rotations per one reciprocal traverse motion, t represents the time in minutes and D represents the thickness of the thread in denier. The above-mentioned winding tightness is created by intentionally increasing the winding yarn tenson and/or increasing the contact pressure of the yarn package with a friction driving roller.