Abstract: A multiprocessor system having a redundant shared memory configuration includes a plurality of processors, each of which are connected to a shared system bus; and a plurality of shared system memory modules, e.g., dual shared system memory modules connected to the shared system bus. A first processor module is operative to write data in one of dual shared system memory modules and subsequently write the data in the other memory module, so as to ensure that the data in both dual shared system memory modules are equivalent to each other. A second processor module monitors a status of the first processor module, and discriminates whether a write operation for the other memory module is finished in normal termination or in abnormal termination in the case where the first processor module stopped operating. The second processor module copies data starting from the address of a first data in the unsuccessfully copied data from the first memory module to the second memory module.

Abstract: The present invention relates to an asynchronous access system for accessing a shared storage in a multiprocessor system in which a plurality of processor modules and shared storage modules are connected through a system bus. The present invention accesses the shared storage at a high speed and reduces the overhead of the system bus. The present invention recognizes in write and read instructions serial access addresses of the shared storage, requests a block access in which a predetermined number of words are grouped as one block, and performs a recovery process when a write instruction is executed abnormally in the block access.

Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A shared storage configuration system for use in a computer system includes a plurality of processing modules. Each of the processing modules includes at least a main storage unit, a central processing unit and a connecting unit for connection to a system bus. The shared storage system also includes a plurality of shared storage modules. Each of the shared storage modules includes a shared storage unit and a connection unit for connection to the system bus. A space inherent in the processing modules is accessible by physical addresses of said central processing unit of each of the processing modules. A shared storage space is accessible by the physical addresses of said central processing unit of each of the processing modules.

Abstract: A shared storage configuration system for use in a computer system includes a plurality of processing modules and a plurality of shared storage modules. Each of the processing modules has at least a main storage unit, a central processing unit, and a connection unit for connection to a system bus. Each of the shared storage modules has a shared storage unit and a connection unit for connection to the system bus. A space inherent in the processing modules is accessible by physical addresses of the central processing units. The shared storage space is accessible either in program mode by the physical addresses of the central processing units or in direct memory access mode by relative addresses translated from the physical addresses output by the central processing units.

Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Abstract: An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

Abstract: An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit recognizes a read from the shared memory module requested from the central processing unit.

Abstract: A message control system is for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit (13) within each processing module (10) includes a data processing part (14) which is a software running on a central processing unit (11) within its own processing module, and a buffer (16, 17) which stores a transmitting message. A connection unit (13) within each processing module (10) at least includes a plurality of logical transmitting ports (21) for successively reading out the message which is expanded in the buffer (16, 17) and transmits the same as a continuous message, a plurality of logical receiving ports (22) for storing the message, a transmission system connecting means (23), and a reception system connecting means (24).

Abstract: In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor writes data into the internal buffer, and the data is read from the internal buffer and is written into the shared memory via the system bus. The asynchronous access system includes a first unit, provided in each of the processor modules, for detecting a predetermined situation regarding a data write from the processor to the shared memory, and a second unit, provided in each of the processor modules, for causing the data stored in the internal buffer to be written into the shared memory module when the first unit detects the predetermined situation.

Abstract: An exclusive control system is provided in a system having a memory module and a plurality of processing modules sharing the memory module, each of the plurality of processing modules exclusively accessing the memory module while prohibiting other processing modules from accessing the memory module. The exclusive control system includes a determination unit for determining whether or not a process executed in response to an access request from a processor module among the plurality of processing modules is normally completed in the memory module, and a retry unit for, when the determination unit determines that the process executed in response to the access request is not normally completed, retrying the process while maintaining a state in which other processing modules are prohibited from accessing the memory module.

Abstract: A message control system for a data communication system in the form of a loosely coupled multiprocessing system, in which a plurality of processing modules having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit, within each processing module, includes a data processing part which is in software running on a central processing unit within its own processing module, a descriptor which manages address and data length information of a storage region for a message in the form of a chain, and a buffer which decomposes and stores a transmitting message. A connection unit within each processing module includes logical transmitting ports and a logical receiving port.

Abstract: A message control system for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In the message control system, each processing module (10, 40) includes a central processing unit (11, 41), a memory unit (12, 42) and a connection unit (13, 43). The connection unit (13, 43) includes at least a logical transmitting port (21, 51) for transmitting a message, a logical receiving port (22, 53) for receiving a message, a transmission system connecting unit (23), a reception system connecting unit (24), a transmitting side fault generation monitoring unit (25) and a receiving side fault generation monitoring unit (26).

Abstract: The present invention comprises a plurality of processor modules and shared storage modules connected through a system bus. It improves system performance by limiting the range and shortening the time of exclusive control when a CSI (compare and store interlocked) instruction is executed to rewrite the contents of a shared storage if read data at an accaccaccess address of a shared storage coincide with the data anticipated by a CPU. In the present invention, when the CPU of the processor module rewrites data by addressing any shared storage module in executing a CSI instruction, the CPU has a connection unit connected through a system bus of a shared storage module recognize the CSI instruction, and reads data and compares them with comparison data in the shared storage module. Thus, the range of the exclusive control is limited to the process in the internal bus in the shared storage module.