Patents by Inventor Akira Kasahara

Akira Kasahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100242837
    Abstract: A combinatorial deposition method is characterized in that, in a method of performing thin-film coating onto a substrate disposed in a vacuum, two or more substrates are moved between a deposition position and a cooling position, sequentially only substrates to be coated is moved to the deposition position while substrates at the cooling position are cooled by a cooling mechanism, and substrates are respectively deposited under different deposition conditions in only one vacuum evacuation process. Various deposition conditions with regard to sputtering and the like are accurately controlled, so that coating films can be efficiently produced under different deposition conditions.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 30, 2010
    Inventors: Masahiro GOTO, Akira Kasahara, Masahiro Tosa
  • Publication number: 20100224278
    Abstract: Two guide pins 11 and 12 formed upright in a guide plate 7 are received in guide pin fitting holes 13 and 14 formed in a guide member 8. Fixed screws 23a and 23b are screw-connected to the guide pins 11 and 12. One guide pin 12 is fitted to the corresponding guide pin fitting hole 14 with a play. Screw holes 20 and 21 are formed through the inner surface of the guide pin fitting hole 14 and the outer surface of the guide member 8. An angle of the guide member 8 with respect to the guide plate 7 is adjusted by allowing front ends of embedded screws 22a and 22b respectively screw-inserted in the screw holes 20 and 21 to respectively engage with a peripheral surface of the guide pin 12.
    Type: Application
    Filed: February 20, 2007
    Publication date: September 9, 2010
    Applicant: MAX CO., LTD.
    Inventors: Ichiro Kusakari, Takahiro Nagaoka, Osamu Itagaki, Akira Kasahara
  • Publication number: 20100147411
    Abstract: A reinforcing bar binding machine is provided with a cutting die having a wire through hole which penetrates through the die along a direction in which a wire is fed out, a blade portion adapted to move along an open plane of an opening at one end of the wire through hole to cut a terminating end portion of the wire which has passed through the wire through hole and an engagement portion adapted to be brought into engagement with a portion of the wire which lies in the vicinity of the terminating end portion thereof when the blade portion is rotated so as to bend to hold the portion lying in the vicinity of the terminating end portion.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 17, 2010
    Applicant: MAX CO., LTD.
    Inventors: Ichiro KUSAKARI, Akira Kasahara
  • Patent number: 7713635
    Abstract: A copper oxide thin film mainly containing CuO is formed by a plasma film-forming process on a substrate for film formation. The friction coefficient of the copper oxide thin film can be controlled remarkably low.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: May 11, 2010
    Assignee: National Institute for Materials Science
    Inventors: Masahiro Goto, Akira Kasahara, Masahiro Tosa, Kazuhiro Yoshihara
  • Publication number: 20100000854
    Abstract: A combinatorial deposition method is characterized in that, in a method of performing thin-film coating onto a substrate disposed in a vacuum, two or more substrates are moved between a deposition position and a cooling position, sequentially only substrates to be coated is moved to the deposition position while substrates at the cooling position are cooled by a cooling mechanism, and substrates are respectively deposited under different deposition conditions in only one vacuum evacuation process. Various deposition conditions with regard to sputtering and the like are accurately controlled, so that coating films can be efficiently produced under different deposition conditions.
    Type: Application
    Filed: September 4, 2009
    Publication date: January 7, 2010
    Inventors: Masahiro GOTO, Akira KASAHARA, Masahiro TOSA
  • Publication number: 20090090428
    Abstract: A reinforcing bar binding machine is provided with a device for detecting a power supply voltage during a binding wire twisting step subjected to the heaviest load and comparing the power supply voltage with a predetermined CPU operation voltage, and a control device for driving a motor in a reverse direction when the voltage has dropped below the predetermined CPU operation voltage. The power supply voltage during operation is monitored, and twisting operation is suspended before the voltage drops below the CPU operation voltage, whereby the binding wire twisting mechanism is returned to the initial position. Therefore, it is possible to prevent the binding wire twisting mechanism from being stopped while grasping the binding wire, when the CPU stops.
    Type: Application
    Filed: June 28, 2006
    Publication date: April 9, 2009
    Applicant: MAX CO., LTD.
    Inventors: Akira Kasahara, Atsushi Matsuoka
  • Patent number: 7498612
    Abstract: A pn-heterojunction compound semiconductor light-emitting device includes a crystalline substrate 101, a lower cladding layer 102 formed on a surface of the crystalline substrate and composed of an n-type Group III-V compound semiconductor, a light-emitting layer 103 formed on a surface of the lower cladding layer and composed of an n-type Group III-V compound semiconductor, an upper cladding layer 105 formed on a surface of the light-emitting layer and composed of p-type boron phosphide, an n-type electrode 106 attached to the lower cladding layer and a p-type electrode 107 attached to the upper cladding layer. The lower and upper cladding layers are opposed to each other and sandwich the light-emitting layer to form, in cooperation with the light-emitting layer, a light-emitting portion of a pn-heterojunction structure. The light-emitting device has an intermediate layer 104 composed of an n-type boron-containing Group III-V compound between the light-emitting layer and the upper cladding layer.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: March 3, 2009
    Assignee: Showa Denko K.K.
    Inventors: Michiya Odawara, Akira Kasahara, Takashi Udagawa
  • Publication number: 20080113219
    Abstract: A copper oxide thin film mainly containing CuO is formed by a plasma film-forming process on a substrate for film formation. The friction coefficient of the copper oxide thin film can be controlled remarkably low.
    Type: Application
    Filed: April 23, 2004
    Publication date: May 15, 2008
    Inventors: Masahiro Goto, Akira Kasahara, Tetsuo Oishi, Masahiro Tosa, Kazuhiro Yoshihara
  • Publication number: 20070131959
    Abstract: A pn-heterojunction compound semiconductor light-emitting device includes a crystalline substrate 101, a lower cladding layer 102 formed on a surface of the crystalline substrate and composed of an n-type Group III-V compound semiconductor, a light-emitting layer 103 formed on a surface of the lower cladding layer and composed of an n-type Group III-V compound semiconductor, an upper cladding layer 105 formed on a surface of the light-emitting layer and composed of p-type boron phosphide, an n-type electrode 106 attached to the lower cladding layer and a p-type electrode 107 attached to the upper cladding layer. The lower and upper cladding layers are opposed to each other and sandwich the light-emitting layer to form, in cooperation with the light-emitting layer, a light-emitting portion of a pn-heterojunction structure. The light-emitting device has an intermediate layer 104 composed of an n-type boron-containing Group III-V compound between the light-emitting layer and the upper cladding layer.
    Type: Application
    Filed: October 22, 2004
    Publication date: June 14, 2007
    Applicant: SHOWA DENKO K.K.
    Inventors: Michiya Odawara, Akira Kasahara, Takashi Udagawa
  • Publication number: 20070111143
    Abstract: To make it possible to fix various organic molecules in an arbitrary configuration or arrangement on a micro/nano scale as a cheap and simple process by irradiating a photocurable resin containing an organic molecule on a substrate with light, thereby curing the photocurable resin in a given pattern and removing an uncured portion, thereby fixing the organic molecule in the given pattern on the substrate.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 17, 2007
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tetsuo Oishi, Masahiro Goto, Akira Kasahara, Masahiro Tosa, Kazuhiro Yoshihara
  • Publication number: 20060118414
    Abstract: A combinatorial deposition method is characterized in that, in a method of performing thin-film coating onto a substrate disposed in a vacuum, two or more substrates are moved between a deposition position and a cooling position, sequentially only substrates to be coated is moved to the deposition position while substrates at the cooling position are cooled by a cooling mechanism, and substrates are respectively deposited under different deposition conditions in only one vacuum evacuation process. Various deposition conditions with regard to sputtering and the like are accurately controlled, so that coating films can be efficiently produced under different deposition conditions.
    Type: Application
    Filed: October 20, 2004
    Publication date: June 8, 2006
    Inventors: Masahiro Goto, Akira Kasahara, Masahiro Tosa
  • Patent number: 6936863
    Abstract: A boron phosphide-based semiconductor light-emitting device, which device includes a light-emitting member having a hetero-junction structure in which an n-type lower cladding layer formed of an n-type compound semiconductor, an n-type light-emitting layer formed of an n-type Group III nitride semiconductor, and a p-type upper cladding layer provided on the light-emitting layer and formed of a p-type boron phosphide-based semiconductor are sequentially provided on a surface of a conductive or high-resistive single-crystal substrate and which device includes a p-type Ohmic electrode provided so as to achieve contact with the p-type upper cladding layer, characterized in that a amorphous layer formed of boron phosphide-based semiconductor is disposed between the p-type upper cladding layer and the n-type light-emitting layer. This boron phosphide-based semiconductor light-emitting device exhibits a low forward voltage or threshold value and has excellent reverse breakdown voltage characteristics.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: August 30, 2005
    Assignee: Showa Denko K.K.
    Inventors: Takashi Udagawa, Akira Kasahara
  • Patent number: 6841435
    Abstract: A GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure are provided wherein, stacked upon a GaAs single-crystal substrate are at least a buffer layer, a GaZIn1-ZAs (0<Z?1) channel layer, and a GaYIn1?YP (0<Y?1) electron-supply layer joined to the channel layer, wherein the GaInP epitaxial stacking structure includes a region within the electron-supply layer wherein the gallium composition ratio (Y) decreases from the side of the junction interface with the channel layer toward the opposite side.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: January 11, 2005
    Assignee: Showa Denko K.K.
    Inventors: Takashi Udagawa, Masahiro Kimura, Akira Kasahara, Taichi Okano
  • Publication number: 20040169184
    Abstract: A boron phosphide-based semiconductor light-emitting device, which device includes a light-emitting member having a hetero-junction structure in which an n-type lower cladding layer formed of an n-type compound semiconductor, an n-type light-emitting layer formed of an n-type Group III nitride semiconductor, and a p-type upper cladding layer provided on the light-emitting layer and formed of a p-type boron phosphide-based semiconductor are sequentially provided on a surface of a conductive or high-resistive single-crystal substrate and which device includes a p-type Ohmic electrode provided so as to achieve contact with the p-type upper cladding layer, characterized in that a amorphous layer formed of boron phosphide-based semiconductor is disposed between the p-type upper cladding layer and the n-type light-emitting layer. This boron phosphide-based semiconductor light-emitting device exhibits a low forward voltage or threshold value and has excellent reverse breakdown voltage characteristics.
    Type: Application
    Filed: November 18, 2003
    Publication date: September 2, 2004
    Applicant: SHOWA DENKO K.K.
    Inventors: Takashi Udagawa, Akira Kasahara
  • Publication number: 20030008440
    Abstract: A GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure are provided wherein, stacked upon a GaAs single-crystal substrate are at least a buffer layer, a GaZIn1−ZAs (0<Z≦1) channel layer, and a GaYIn1−YP (0<Y≦1) electron-supply layer joined to the channel layer, wherein the GaInP epitaxial stacking structure includes a region within the electron-supply layer wherein the gallium composition ratio (Y) decreases from the side of the junction interface with the channel layer toward the opposite side.
    Type: Application
    Filed: July 9, 2002
    Publication date: January 9, 2003
    Applicant: SHOWA DENKO K.K.
    Inventors: Takashi Udagawa, Masahiro Kimura, Akira Kasahara, Taichi Okano
  • Patent number: 6462361
    Abstract: A GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure are provided wherein, stacked upon a GaAs single-crystal substrate are at least a buffer layer, a GaZIn1−ZAs (0<Z≦1) channel layer, and a GaYIn1−YP (0<Y≦1) electron-supply layer joined to the channel layer, wherein the GaInP epitaxial stacking structure includes a region within the electron-supply layer wherein the gallium composition ratio (Y) decreases from the side of the junction interface with the channel layer toward the opposite side.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: October 8, 2002
    Assignee: Showa Denko K.K.
    Inventors: Takashi Udagawa, Masahiro Kimura, Akira Kasahara, Taichi Okano
  • Patent number: 5262182
    Abstract: A breadmaking dough conditioner is disclosed which comprises (a) an ascorbic acid, (b) at least one amino acid or salts thereof selected from the group consisting of cystine, methionine, asparagic acid, alanine, glycine and salts thereof, (c) an alum and (d) at least one emulsifier selected from the group consisting of a glycerol fatty acid monoester and a sucrose fatty acid ester having an HLB value of 5 to 10. The dough conditioners are especially suitable for the manufacture of bread using a frozen or chilled bread dough. They can prepare breads which have no fisheyes on the surface of the baked bread, have large bread volume and are good in all respects of appearance, inner phase, taste and flavor.
    Type: Grant
    Filed: August 3, 1992
    Date of Patent: November 16, 1993
    Assignee: Nisshin Flour Milling Co., Ltd.
    Inventors: Akira Kasahara, Koji Takeya, Hiroshi Takeshima, Ryuji Uemura