Patents by Inventor Akira Katakami
Akira Katakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865734Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: December 13, 2016Date of Patent: January 9, 2018Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9728468Abstract: A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.Type: GrantFiled: December 28, 2015Date of Patent: August 8, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Akira Katakami
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Publication number: 20170117412Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: December 13, 2016Publication date: April 27, 2017Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9577098Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: June 22, 2016Date of Patent: February 21, 2017Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20160308053Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: June 22, 2016Publication date: October 20, 2016Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9401427Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: June 23, 2015Date of Patent: July 26, 2016Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20160133527Abstract: A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Inventor: Akira Katakami
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Patent number: 9257425Abstract: A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.Type: GrantFiled: June 3, 2014Date of Patent: February 9, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Akira Katakami
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Publication number: 20150295086Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: June 23, 2015Publication date: October 15, 2015Applicant: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9112027Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: August 26, 2014Date of Patent: August 18, 2015Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20140367791Abstract: A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.Type: ApplicationFiled: June 3, 2014Publication date: December 18, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Akira Katakami
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Publication number: 20140361340Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: August 26, 2014Publication date: December 11, 2014Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 8853673Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: May 15, 2013Date of Patent: October 7, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 8786022Abstract: A semiconductor device includes a gate insulation film formed over a semiconductor substrate; a cap film formed over the gate insulation film; a silicon oxide film formed over the cap film; a metal gate electrode formed over the silicon oxide film; and source/drain diffused layers formed in the semiconductor substrate on both sides of the metal gate electrode.Type: GrantFiled: March 21, 2011Date of Patent: July 22, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Akira Katakami, Takayuki Aoyama
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Publication number: 20140051222Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, patterning the first insulating film to form a first and a second opening, forming a first sidewall film on side walls of the first and the second openings, etching the semiconductor substrate with the first insulating film and the first sidewall film as a mask to dig down the first opening and the second opening, removing the first sidewall film to form a first offset portion in the first opening and a second offset portion in the second opening, the first and the second offset portion including a part of a surface of the semiconductor substrate, and etching a bottom of the first opening with the first insulating film as a mask.Type: ApplicationFiled: August 9, 2013Publication date: February 20, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: MASANORI TERAHARA, Akira Katakami, Eiji Yoshida, AKIHIKO HARADA
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Patent number: 8575704Abstract: A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.Type: GrantFiled: March 8, 2012Date of Patent: November 5, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Masaki Haneda, Akiyoshi Hatada, Akira Katakami, Yuka Kase, Kazuya Okubo
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Publication number: 20130248930Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: May 15, 2013Publication date: September 26, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 8518785Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.Type: GrantFiled: September 5, 2012Date of Patent: August 27, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Yosuke Shimamune, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
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Patent number: 8466450Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: July 29, 2010Date of Patent: June 18, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 8421155Abstract: A semiconductor device includes a first device isolation insulating film formed in a semiconductor substrate, a first well having a first conductivity type, defined by the first device isolation insulating film, and shallower than the first device isolation insulating film, a second device isolation insulating film formed in the first well, shallower than the first well, and defining a first part of the first well and a second part of the first well, a gate insulating film formed above the first part, a gate electrode formed above the gate insulating film, and an interconnection electrically connected to the second part of the first well and the gate electrode, wherein an electric resistance of the first well in a first region below the second device isolation insulating film is lower than an electric resistance of the first well in a second region other than the first region on the same depth level.Type: GrantFiled: December 2, 2011Date of Patent: April 16, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Akira Katakami, Eiji Yoshida