Patents by Inventor Akira Kikutake
Akira Kikutake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060156214Abstract: Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.Type: ApplicationFiled: March 30, 2005Publication date: July 13, 2006Inventors: Akira Kikutake, Kuninori Kawabata
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Patent number: 7075834Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.Type: GrantFiled: November 28, 2001Date of Patent: July 11, 2006Assignees: Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Kuninori Kawabata, Akira Kikutake, Shinichiro Shiratake
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Publication number: 20060133166Abstract: Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.Type: ApplicationFiled: June 20, 2005Publication date: June 22, 2006Inventors: Akira Kikutake, Yasuhiro Onishi, Kuninori Kawabata, Junichi Sasaki, Toshiya Miyo
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Publication number: 20060136800Abstract: A memory system that can enhance yield without increasing the chip size and without degrading the access time. A single-bit error determination circuit references parity bits required to configure a code capable of correcting a single-bit error, and determines a single-bit error to be corrected; and a double-bit error detection circuit references one redundant bit added to the parity bits, detects a double-bit error, and enables or disables the double-bit error detection in accordance with a selection signal.Type: ApplicationFiled: March 25, 2005Publication date: June 22, 2006Inventors: Kuninori Kawabata, Satoshi Eto, Yasuhiro Onishi, Akira Kikutake
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Publication number: 20050190618Abstract: A semiconductor memory device includes a plurality of first fuse latch circuits configured to provide redundancy to first addresses, a plurality of second fuse latch circuits configured to provide redundancy to second addresses, and a nullifying circuit configured to make the plurality of second fuse latch circuits ineffective, wherein first fuse positions corresponding to the plurality of first fuse latch circuits intervene between second fuse positions corresponding to the plurality of second fuse latch circuits.Type: ApplicationFiled: April 25, 2005Publication date: September 1, 2005Inventors: Akira Kikutake, Shigemasa Ito, Kuninori Kawabata
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Publication number: 20050185465Abstract: A memory device includes plural banks (BNKA, BNKB, BNKC, and BNKD), and each of the banks includes a plural memory cells storing data and plural bit lines reading data from the plural memory cells. Bit line lengths of all of the plural banks are equal.Type: ApplicationFiled: April 21, 2005Publication date: August 25, 2005Inventors: Nobutaka Taniguchi, Atsushi Hatakeyama, Toshimi Ikeda, Akira Kikutake, Kuninori Kawabata, Atsushi Takeuchi
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Publication number: 20050162955Abstract: A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells each holding memory cell information are arrayed, reference cells which supply different reference currents respectively, and a read-out circuit. When reading the memory cell information from a selected one of the memory cells, the read-out circuit is brought into conduction to a first global bit line which is connected to a bit line of the selected memory cell, and brought into conduction to one of a plurality of second global bit lines respectively which are provided near the first global bit line and connected to bit lines of non-selected memory cells but not connected to the bit line of the selected memory cell, so that the memory cell information is determined by comparing a read-out current from the selected memory cell with each of the reference currents from the reference cells.Type: ApplicationFiled: February 24, 2005Publication date: July 28, 2005Inventors: Toshimi Ikeda, Atsushi Hatakeyama, Nobutaka Taniguchi, Akira Kikutake, Kuninori Kawabata, Atsushi Takeuchi
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Publication number: 20050141306Abstract: A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.Type: ApplicationFiled: March 3, 2005Publication date: June 30, 2005Inventors: Atsushi Hatakeyama, Toshimi Ikeda, Nobutaka Taniguchi, Akira Kikutake, Kuninori Kawabata, Atsushi Takeuchi
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Patent number: 6671220Abstract: A semiconductor device includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.Type: GrantFiled: March 13, 2002Date of Patent: December 30, 2003Assignee: Fujitsu LimitedInventors: Akira Kikutake, Satoshi Eto
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Patent number: 6643805Abstract: The present invention is a memory circuit which selects N number of segments out of M number of segments (N<M) during normal reading, wherein all the M number of segments are activated during a read test in order to drive a common data bus for testing by a plurality of sense buffers in the M number of segments. For this, test signals are supplied to a column decoder, and segment select signals, for activating the M number of segments, are generated in response to the test signal. In this way, a plurality of segments in a memory bank in a select status can be simultaneously selected to execute a read test, and the efficiency of a compression read test can be improved.Type: GrantFiled: May 10, 2000Date of Patent: November 4, 2003Assignee: Fujitsu LimitedInventors: Akira Kikutake, Masato Matsumiya, Satoshi Eto, Kuninori Kawabata
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Publication number: 20030048690Abstract: A semiconductor device includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.Type: ApplicationFiled: March 13, 2002Publication date: March 13, 2003Applicant: FUJITSU LIMITEDInventors: Akira Kikutake, Satoshi Eto
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Patent number: 6477074Abstract: Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.Type: GrantFiled: September 26, 2001Date of Patent: November 5, 2002Assignees: Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Akira Kikutake, Shinichiro Shiratake, Kuninori Kawabata
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Publication number: 20020067642Abstract: Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.Type: ApplicationFiled: September 26, 2001Publication date: June 6, 2002Applicant: FUJITSU LIMITEDInventors: Akira Kikutake, Shinichiro Shiratake, Kuninori Kawabata
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Publication number: 20020067647Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.Type: ApplicationFiled: November 28, 2001Publication date: June 6, 2002Applicant: Fujitsu Limited and Kabushiki Kaisha ToshibaInventors: Kuninori Kawabata, Akira Kikutake, Shinichiro Shiratake
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Patent number: 6226203Abstract: It is one aspect of the present invention to split a common data bus established in common for a plurality of segments into a read-dedicated common data bus and a write dedicated common data bus, in a memory device comprising a plurality of segments each of which includes a plurality of memory cells. With such a constitution, write data can be supplied to the write data bus even when read data are present on the read common data bus due to a read operation; and even when operation frequencies increase, there are no limitations to the timing of write operations following reading and the speed of write operations following reading can be increased.Type: GrantFiled: February 11, 2000Date of Patent: May 1, 2001Assignee: Fujitsu LimitedInventors: Akira Kikutake, Masato Matsumiya, Satoshi Eto, Kuninori Kawabata
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Patent number: 6212091Abstract: A semiconductor memory device has data bus lines which are connected to a memory cell array, and column selection lines, each of which is used to select a column of the memory cell array. The semiconductor memory device includes a shielding line placed between the column selection line and a data bus line adjacent to the column selection line. The shielding line electrically shields the data bus line from the column selection line. Therefore, the semiconductor memory device having the high speed data bus can be achieved because the coupling capacitance between the column selection line and the data bus line is reduced.Type: GrantFiled: February 28, 2000Date of Patent: April 3, 2001Assignee: Fujitsu LimitedInventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Akira Kikutake
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Patent number: 6195304Abstract: A semiconductor memory device includes a memory cell array having a number of memory cells configured in a square or rectangular formation, the memory cell array having predetermined capacitive loads which are different at different memory locations, the capacitive loads including a smallest capacitive load and a largest capacitive load. A refresh address counter outputs a number of bit signals which constitute a refresh address signal, the refresh address signal indicating an address of a memory cell to be refreshed in the memory device, the bit signals having predetermined high/low-state change periods which are different from each other, the bit signals including a first bit signal corresponding to the smallest capacitive load and a second bit signal corresponding to the largest capacitive load.Type: GrantFiled: February 10, 2000Date of Patent: February 27, 2001Assignee: Fujitsu LimitedInventors: Satoshi Eto, Masato Matsuyima, Kuninori Kawabata, Akira Kikutake
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Patent number: 6188625Abstract: For cutting off a path for flowing a read detection current from a high-potential power supply (Vii) of a read data bus amplifier (S/B 33) to the ground side of a read controller (41) via a sense amplifier (31) selected based on an address in a write to a memory cell, a semiconductor memory device have a logic circuit (42, 43) for calculating logic between a block select signal and a write status signal to change the potential at the read controller (41) to the same power supply potential as that at the S/B (33) when the write status signal is activated. This logic circuit can prevent any unwanted read detection current from flowing in a data write, so as to suppress current consumption in a write.Type: GrantFiled: December 16, 1999Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Akira Kikutake
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Patent number: 6147919Abstract: A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks.Type: GrantFiled: March 23, 1999Date of Patent: November 14, 2000Assignee: Fujitsu LimitedInventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Masatomo Hasegawa, Hideki Kanou, Ayako Kitamoto, Toru Koga, Yuki Ishii, Akira Kikutake, Yuichi Uzawa
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Patent number: 6141274Abstract: In a semiconductor integrated circuit having the function of executing a pre-charge operation of a data bus when data is transferred to the data bus from a plurality of driver circuits connected to the data bus, a reset circuit for executing the pre-charge operation of the data bus is constituted so as to start the pre-charge operation of the data bus upon receiving an end timing of a strobe signal. Preferably, the reset circuit detects that the data bus reaches a pre-charge level for executing the pre-charge operation, and then terminates the pre-charge operation. On the other hand, in a semiconductor integrated circuit having a data latch function by a pipeline system when the data is read out from a memory cell, etc.Type: GrantFiled: June 28, 1999Date of Patent: October 31, 2000Assignee: Fujitsu LimitedInventors: Satoshi Eto, Masato Matsumiya, Yuichi Uzawa, Kuninori Kawabata, Akira Kikutake, Toru Koga