Abstract: This invention provides a low-cost, economical printing apparatus and printing system. For example, characteristic information of a printhead which is described, printed, adhered, or formed on a printhead or its accessory (e.g., a packaging paper box) in a format identifiable to human or an electronic device is man-machine-interactively inputted to a host or electronically inputted to the host by a barcode reader or the like. The printing apparatus discriminates whether or not a command sent from the host via an interface is a command that includes characteristic information of the printhead, and control is made to write the characteristic information of the print head into a non-volatile memory (EEPROM) in accordance with the discriminating result. The printhead is controlled in accordance with the characteristic information written into the non-volatile memory to execute a print process.

Abstract: A motor control apparatus has a motor driver for driving a motor in accordance with an input of digital-format drive data of a predetermined length, thereby driving a mechanism using the motor as a power source. The drive data, which has been made to correspond to a plurality of drive patterns, is stored in a memory, part of the drive data, which has been read out from the memory by DMA, is replaced with other data, and the resultant data is output to the motor driver. Thus, different drive data can be generated by replacing a part of the drive data stored in the memory with other data, and the generated data can be transferred to the motor driver. This makes it possible to reduce the memory capacity needed for motor control.

Abstract: There is provided an output control circuit provided in an integrated circuit that enables any arbitrary internal signal to be specified and output from any output terminal, and hence enable the monitoring of a large number of internal signals even if only a small number of output terminals are provided. A plurality of external output terminals output a plurality of signals existing in the integrated circuit. A plurality of signal output circuits are provided, to which the plurality of internal signals are mutually input. Each of the signal output circuits comprises a signal group select circuit that selects a predetermined signal group from the plurality of internal signals, a logic circuit that carries out logical operations on the selected signal group, and an external output circuit that outputs signals resulting from the logical operations via one of the external output terminals.

Abstract: Printing data containing a flag representing the type of printing mode is input from a host computer via an interface. An MPU selects either of print buffer 1 and print buffer 2 as a storage destination serving as a printing data holding destination on the basis of the flag in the input printing data that represents the type of printing mode. The printing data is stored in the selected storage destination. The stored printing data is transferred to a printhead.

Abstract: A printer, which enables complicated printhead controls without a complicated logic circuit, includes a data table showing a control pattern of six controls stored in a RAM. When a drive trigger is inputted into a read-trigger generator, an address generator generates the address of the data table in the RAM as an address signal and inputs the address signal into the RAM. On the other hand, the read-trigger generator inputs a data-read trigger into the RAM. Control signals read by these signals are inputted into a head driver with heat pulses, which drives the printhead.

Abstract: A DMA controller arbitrates and selects a DMA control information signal received from at least one of a plurality of DMA request blocks and accesses an SDRAM on the basis of the selected DMA control information signal. In the DMA controller, an SDRAM controller detects using a detector the number of possible sequential accesses on the basis of a DMA start address signal, compares using a comparator this number of possible sequential accesses with the burst DMA request number designated by a BSTNUM signal, selects not larger one of the two numbers, and sets the number of sequential DMAs to be actually executed to the selected number. Accordingly, with a simple configuration, sequential access is made possible starting from an arbitrary address.

Abstract: A CPU monitors the state of a printing apparatus, and controls transmission, to the host, of a control signal for controlling the data reception timing from the host.

Abstract: A motor control apparatus has a motor driver for driving a motor in accordance with an input of digital-format drive data of a predetermined length, thereby driving a mechanism using the motor as a power source. The drive data, which has been made to correspond to a plurality of drive patterns, is stored in a memory, part of the drive data, which has been read out from the memory by DMA, is replaced with other data, and the resultant data is output to the motor driver. Thus, different drive data can be generated by replacing a part of the drive data stored in the memory with other data, and the generated data can be transferred to the motor driver. This makes it possible to reduce the memory capacity needed for motor control.

Abstract: To reduce the data processing load on a recording apparatus, an information processing apparatus and the recording apparatus cooperate to correct registration errors. The information processing apparatus divides a recording area of the recording apparatus into a plurality of partial areas and makes a first correction on a recording position of image data for each partial area; the correction is made for color data items and in pixels. The information processing apparatus generates image data that conforms to the corrected recording position, as well as setting information for controlling the recording apparatus to record the image data (S115). The recording apparatus makes a second correction on the recording position of the image data in fractions of a pixel based on the setting information generated by the information processing apparatus and controls recording of the image data based on the corrected recording position (S125).

Abstract: A recording apparatus has a buffer for dividing a storage area into a plurality of areas in a scanning direction of a recording head to record data by allowing a carriage loaded with the recording head to scan data on a record medium, and storing the divided image data in a divided area unit, and includes: a write control unit for controlling write address information about image data in the area unit for data of each color for storage of the image data divided in an area unit in the buffer; a read control unit for controlling for data of each color read address information for a read of image data stored in the buffer; and a record data generation unit for generating record data in a unit of the divided area based on the read image data according to the read address information.

Abstract: A recording apparatus for recording with use of a recording head having two nozzle arrays arranged side-by-side includes first, second, and third direct memory access (DMA) units, a data converter unit for converting first image data stored in a work buffer into second image data, a record buffer unit for storing the second image data, a latch unit for storing the second image data in a transfer buffer, a buffer reading control table unit, and a DMA control unit for causing transfer processing to be executed by the first, second, and third DMA units based on a flag in the buffer reading control table unit when the image data stored in the work buffer is transferred to the transfer buffer.

Abstract: A recording apparatus and a signal control method for the recording apparatus capable of high speed data reception suitable for each host apparatus and an improved throughput. The recording apparatus is provided with an interface control block and a CPU, the former transmitting an ACKX signal representative of a completion of data reception from a host apparatus to the host apparatus, and the latter controlling not to output the ACKX signal if it is judged that the ACKX signal is unnecessary, and to output the ACKX signal with an optimum width if it is judged that the ACKX signal is necessary.

Abstract: A recording apparatus and a signal control method for the recording apparatus capable of high speed data reception suitable for each host apparatus and an improved throughput. The recording apparatus is provided with an interface control block and a CPU, the former transmitting an ACKX signal representative of a completion of data reception from a host apparatus to the host apparatus, and the latter controlling not to output the ACKX signal if it is judged that the ACKX signal is unnecessary, and to output the ACKX signal with an optimum width if it is judged that the ACKX signal is necessary.

Abstract: There is provided an output control circuit provided in an integrated circuit that enables any arbitrary internal signal to be specified and output from any output terminal, and hence enable the monitoring of a large number of internal signals even if only a small number of output terminals are provided. A plurality of external output terminals output a plurality of signals existing in the integrated circuit. A plurality of signal output circuits are provided, to which the plurality of internal signals are mutually input. Each of the signal output circuits comprises a signal group select circuit that selects a predetermined signal group from the plurality of internal signals, a logic circuit that carries out logical operations on the selected signal group, and an external output circuit that outputs signals resulting from the logical operations via one of the external output terminals.

Abstract: Disclosed is a printing apparatus in which printing elements used in the printing of each raster can be set at will. The printing apparatus has a carriage equipped with a printhead having a plurality of printing elements arranged in a predetermined direction, and the carriage is made to scan across a printing medium in a direction that intersects the direction in which the printing elements are arranged, thereby performing printing on the medium. The printing elements are divided into a plurality of blocks each consisting of a predetermined number of successive printing elements, print data that has been transmitted in raster form is stored in a receive buffer, and data that has been stored in the receive buffer is divided and stored in a print buffer having a plurality of areas corresponding to the blocks of printing elements.

Abstract: This invention provides a low-cost, economical printing apparatus and printing system. For example, characteristic information of a printhead which is described, printed, adhered, or formed on a printhead or its accessory (e.g., a packaging paper box) in a format identifiable to human or an electronic device is man-machine-interactively inputted to a host or electronically inputted to the host by a barcode reader or the like. The printing apparatus discriminates whether or not a command sent from the host via an interface is a command that includes characteristic information of the printhead, and control is made to write the characteristic information of the print head into a non-volatile memory (EEPROM) in accordance with the discriminating result. The printhead is controlled in accordance with the characteristic information written into the non-volatile memory to execute a print process.

Abstract: A printer which enables a complicated printhead controls without complicated logic circuit. In this printer, a data table showing a control pattern of six control signals (COM11, COM12, COM21, COM22, UPPER ENABLE and LOWER ENABLE) is stored in RAM 74. When a drive trigger is inputted into read-trigger generator 71, address generator 72 generates the address of the data table in the RAM 74 as address signal AD1 and inputs the address signal into the RAM 74. On the other hand, read-trigger generator 71 inputs a data-read trigger into RAM 74. Control signals read by these signals are inputted into head driver 75 with heat pulses, which drives the printhead.

Abstract: A printer and printing control method for improving throughput by performing efficient smoothing processing. The printer adopting the method monitors print data while it is transmitted from a receiving buffer 25a to a print buffer 25b, analyses the print data by a unit of one scanning area of a printhead whether the print data causes printing operation of the printhead, and, if no print data which causes printing operation is included in the print data corresponding to the one scanning area, controls to skip execution of row-column conversion and/or smoothing processing.

Abstract: When the sub-heaters of recording heads are PWM controlled in a low-temperature environment, temperatures of the recording heads are respectively detected by temperature sensors. The number of recording heads to be heating controlled is determined from the detected recording head temperatures, and a maximum duty ratio of a pulse train supplied to the sub-heater corresponding to the recording head to be heating controlled is determined in accordance with the determined number of the recording heads, so that supply timings of pulse width controlled pulse trains supplied to the sub-heaters corresponding to the recording heads to be heating controlled are not overlapped.

Abstract: A data processing method which efficiently performs data transfer by using a data bus with an appropriate access width corresponding to transfer data and a printer using the data processing method. In the printer, a CPU bus 70 having a 16-bit physical bus width, is shared by a CPU 21 and a DMAC 80. In a case where the CPU 21 accesses a memory via the CPU bus 70 with an 8-bit width, while the DMAC 80 accesses the memory via the CPU bus 70 with a 16-bit width, each time the DMAC 80 needs to access the memory, the DMAC 80 issues a DMA request signal to the CPU 21, requiring an exclusive access right for the CPU bus 70. In accordance with the request signal, the CPU 21 delivers the exclusive access right for the CPU bus 70 to the DMAC 80. Then the DMAC 80 controls memory access with the 16-bit width.