Patents by Inventor Akira Matsunami

Akira Matsunami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7550852
    Abstract: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each end and a layer of reflowable material on each end. Each member is solder-attached at one end to a chip contact pad, while the other end of each member is operable for reflow attachment to external parts.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 23, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: John P Tellkamp, Akira Matsunami
  • Publication number: 20090085207
    Abstract: The invention provides ball grid array assemblies and methods for their manufacture, with improved characteristics favoring the formation of secure metallurgical solder pad to solder ball joints. In disclosed preferred embodiments of ball grid array assemblies, substrates, and methods according to the invention, solder pads are provided with metal blocks comprising a layer primarily of nickel plated with an outer metal layer comprising primarily gold.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventor: Akira Matsunami
  • Publication number: 20090075404
    Abstract: According to one embodiment of the invention, a method of testing ball grid array packages includes providing a substrate, providing a ball film that includes a plurality of metal balls movably contained within respective slots of a thin film, coupling the metal balls to the substrate, and removing the thin film from the metal balls.
    Type: Application
    Filed: October 13, 2008
    Publication date: March 19, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Akira Matsunami
  • Publication number: 20080299685
    Abstract: In a method and system for assembling a semiconductor device, a tray is configured to provide an array of bins arranged in m rows and n columns, where m and n are integers. The tray containing defect free singulated substrates is received from a substrate supplier for assembly. Each one of the defect free singulated substrates, which is disposed in a corresponding bin of the tray, is accessible in a concurrent or sequential manner, thereby enabling concurrent or sequential assembly of m*n ones of the defect free singulated substrate. The assembly process for the semiconductor device starting from the defect free singulated substrate includes die attach, wire bonding, mold press, laser marking, solder ball attach, and testing operations. Assembly of the defect free singulated substrates avoids material loss and increases manufacturing efficiency.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Applicant: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Publication number: 20080290885
    Abstract: In a method and system for testing a device under test (DUT), a replaceable test connector (RTC) is disposed between a probe pin of a tester and the DUT. The RTC includes an upper test bond pad that is electrically coupled to a lower test bond pad. The probe pin is capable of being positioned to make a physical contact with the upper test bond pad, the physical contact enabling an electrical coupling there between. The lower test bond pad is capable of being positioned to make physical contact with a device bond pad of the DUT, the physical contact enabling an electrical coupling between the lower test bond pad and the device bond pad. The device bond pad is protected from potential damage from the probe pin by the RTC that is replaceable.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Applicant: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Patent number: 7452799
    Abstract: According to one embodiment of the invention, a method of fabricating ball grid array packages includes providing a substrate, providing a ball film that includes a plurality of metal balls movably contained within respective slots of a thin film, coupling the metal balls to the substrate, and removing the thin film from the metal balls.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: November 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Patent number: 7439612
    Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: October 21, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Publication number: 20080153208
    Abstract: Semiconductor device packages and methods related to their manufacture are described in which improved block molds and block-molding methods alleviate warpage in semiconductor device manufacturing processes. Preferred embodiments of the invention are disclosed in which semiconductor device package manufacturing includes placing an array of chips mounted on a substrate within a mold. The mold is configured for encapsulating the chip and substrate array, and has features for excluding mold compound from selected areas to form ditches in the cured mold compound. The ditches act to reduce warpage. After removal from the mold, the block-molded array is singulated into individual semiconductor device packages.
    Type: Application
    Filed: January 11, 2007
    Publication date: June 26, 2008
    Inventor: Akira Matsunami
  • Patent number: 7371673
    Abstract: A technique for attaching solder balls of a BGA to a PCB. In one example embodiment, this is accomplished by applying solder paste onto at least one of a plurality of contact pads on a PCB. At least one of a plurality of solder balls of an IC device are then onto the at least one of the plurality of contact pads on the PCB. The temperature is then increased to reflow the solder paste. The IC device is then pulled away from the PCB as a function of a geometric shape of the IC device and held in a new position upon reflowing the solder paste to transform the at least one of the plurality of solder balls and the reflowed solder paste into a high shear strength solder joint structure. The reflow temperature is then lowered to room temperature to attach the high shear strength solder joint structure to the at least one of the plurality of lands on the PCB.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: May 13, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Publication number: 20080006937
    Abstract: A microelectronic device package that includes a microelectronic device encapsulated within a packaging material. The microelectronic device package also includes a lead attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.
    Type: Application
    Filed: June 23, 2006
    Publication date: January 10, 2008
    Applicant: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Patent number: 7220606
    Abstract: A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor wafer in proximity to the reticle; directing radiation through a first plurality of the pixels onto a first location on the wafer; changing the relative positions of the semiconductor wafer and the reticle; and directing radiation through a second plurality of the pixels onto a second location on the wafer. The first plurality of pixels can be used to form a first mark and the second plurality of pixels can be used to form a second mark, wherein the second mark is different from the first mark. The marks can be made of a pattern of dots in order to save space. The pixels can be selected to form certain marks by using a computer 304 to turn on or off a transistor that may be associated with each pixel. Also described is a system for marking a semiconductor wafer.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: May 22, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Publication number: 20070034996
    Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.
    Type: Application
    Filed: October 2, 2006
    Publication date: February 15, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Akira Matsunami
  • Publication number: 20070018304
    Abstract: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each end and a layer of reflowable material on each end. Each member is solder-attached at one end to a chip contact pad, while the other end of each member is operable for reflow attachment to external parts.
    Type: Application
    Filed: September 6, 2006
    Publication date: January 25, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: John Tellkamp, Akira Matsunami
  • Publication number: 20060263929
    Abstract: A technique for attaching solder balls of a BGA to a PCB. In one example embodiment, this is accomplished by applying solder paste onto at least one of a plurality of contact pads on a PCB. At least one of a plurality of solder balls of an IC device are then onto the at least one of the plurality of contact pads on the PCB. The temperature is then increased to reflow the solder paste. The IC device is then pulled away from the PCB as a function of a geometric shape of the IC device and held in a new position upon reflowing the solder paste to transform the at least one of the plurality of solder balls and the reflowed solder paste into a high shear strength solder joint structure. The reflow temperature is then lowered to room temperature to attach the high shear strength solder joint structure to the at least one of the plurality of lands on the PCB.
    Type: Application
    Filed: May 17, 2005
    Publication date: November 23, 2006
    Inventor: Akira Matsunami
  • Publication number: 20060258141
    Abstract: According to one embodiment of the invention, a method of fabricating ball grid array packages includes providing a substrate, providing a ball film that includes a plurality of metal balls movably contained within respective slots of a thin film, coupling the metal balls to the substrate, and removing the thin film from the metal balls.
    Type: Application
    Filed: May 31, 2006
    Publication date: November 16, 2006
    Inventor: Akira Matsunami
  • Patent number: 7132314
    Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Patent number: 7125789
    Abstract: An integrated circuit chip 903, which has a plurality of pads 903b and non-reflowable contact members 1201 to be connected by reflow attachment to external parts. Each of these contact members 1201 has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface 1202 on each end and a layer of reflowable material on each end. Each member is solder-attached (1204) at one end to a chip contact pad 903b, while the other end (1203) of each member is operable for reflow attachment to external parts.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: October 24, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: John P. Tellkamp, Akira Matsunami
  • Patent number: 7078821
    Abstract: According to one embodiment of the invention, a method of fabricating ball grid array packages includes providing a substrate, providing a ball film that includes a plurality of metal balls movably contained within respective slots of a thin film, coupling the metal balls to the substrate, and removing the thin film from the metal balls.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: July 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Publication number: 20060091516
    Abstract: A multi-chip semiconductor device comprises two semiconductor assemblies vertically aligned so that the second active chip surface (110a) faces the first active chip surface (101a) and forms a gap (120) between the assemblies. Encapsulation material (130) fills the gap and couples the first and second assemblies together to form the multi-chip device (100). Lead portions of the first and second leadframes remain exposed from the encapsulation material. The exposed leads (104) of the first leadframe may be comprised for leadless assembly, and the exposed leads (114a) of the second leadframe may be formed coplanar with the first leads (104).
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventor: Akira Matsunami
  • Publication number: 20060022339
    Abstract: A ball grid array (“BGA”) package substrate, comprising a metallic core, a layer of copper abutting at least a portion of said core, a layer of nickel abutting at least a portion of the layer of copper, a layer of gold abutting at least some of the layer of nickel, and a solder ball opening abutting at least some of the layer of gold, wherein the solder ball opening comprises a protrusion, said protrusion comprising an inner copper layer, an outer gold layer, and a nickel layer situated therebetween.
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Akira Matsunami