Patents by Inventor Akira MINO

Akira MINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230320107
    Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Applicant: Kioxia Corporation
    Inventors: Keisuke NAKATSUKA, Yasuhiro UCHIYAMA, Akira MINO, Masayoshi TAGAMI, Shinya ARAI
  • Publication number: 20230075993
    Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a first conductive layer, and a second conductive layer arranged in this order in a first direction and separated from each other, a first semiconductor film extending in the first direction, intersecting the first conductive layer, and being in contact with the second conductive layer, and a first charge storage film arranged between the first semiconductor film and the first conductive layer, and being in contact with the second conductive layer, wherein the first semiconductor film includes a first portion formed of an n-type semiconductor at approximately a same height as the first conductive layer.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Koichi SAKATA, Shinya ARAI, Susumu HASHIMOTO, Akira MINO, Shunsuke OKADA, Keisuke NAKATSUKA
  • Patent number: 10950615
    Abstract: A semiconductor memory device of embodiments includes a semiconductor substrate having a first and a second region adjacent to the first region in a first direction, a laminated body including electrode layers laminated on the semiconductor substrate in a second direction, a first insulator splitting the laminated body at the second region in a third direction, and extending in the first and second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body, a contact portion extending in the first portion in the second direction, and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion is wider than a second width in the third direction of at least one of the electrode layers at the second region.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 16, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Watanabe, Akira Mino, Masahisa Sonoda, Takashi Shimizu
  • Publication number: 20190386018
    Abstract: A semiconductor memory device of embodiments includes a semiconductor substrate having a first and a second region adjacent to the first region in a first direction, a laminated body including electrode layers laminated on the semiconductor substrate in a second direction, a first insulator splitting the laminated body at the second region in a third direction, and extending in the first and second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body, a contact portion extending in the first portion in the second direction, and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion is wider than a second width in the third direction of at least one of the electrode layers at the second region.
    Type: Application
    Filed: March 7, 2019
    Publication date: December 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yuta WATANABE, Akira Mino, Masahisa Sonoda, Takashi Shimizu
  • Patent number: 9151378
    Abstract: When a MODE selector SW is manipulated while CVT automatic shifting mode is selected, the shifting mode is switched to STEP-AT automatic shifting mode. Then, when the shift lever of a shifting device is manipulated by the driver while the CVT automatic shifting mode is selected as the shifting mode of a CVT, the then-set automatic shifting control mode for the CVT is maintained whereas the shifting mode of the CVT is switched to sport mode. When the sport mode being selected as the shifting mode of the CVT is canceled, the shifting mode of the CVT is switched to the mode selected before the switchover to the sport mode, that is, the maintained automatic shifting control mode, unless the MODE selector SW is manipulated during execution of the sport mode.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 6, 2015
    Assignees: MITSUBISHI JIDOSHA ENGINEERING KABUSHIKI KAISHA, MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Akira Mino, Seiichi Inukai
  • Patent number: 9012972
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisakazu Matsumori, Hideto Takekida, Akira Mino, Jun Murakami
  • Publication number: 20150069485
    Abstract: A semiconductor device includes memory cell units, each including memory cell transistors, a first transistor at a first end of the memory cell transistors, and a second transistor at a second end of the memory cell transistors. The memory cell units are arranged so that adjacent memory cell units have first transistors thereof facing each other or second transistors thereof facing each other, and so that a distance between the first transistors of the adjacent memory cell units is larger than a distance between the second transistors of the adjacent memory cell units. The semiconductor device further includes a first silicon nitride layer covering a first diffusion layer of the first transistors, a second silicon nitride layer covering a second diffusion layer of the second transistors. A thickness of the second silicon nitride layer is smaller than a thickness of the first silicon nitride layer.
    Type: Application
    Filed: March 3, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira YOTSUMOTO, Kotaro FUJII, Hideki INOKUMA, Akira MINO
  • Publication number: 20140231896
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.
    Type: Application
    Filed: September 6, 2013
    Publication date: August 21, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisakazu MATSUMORI, Hideto TAKEKIDA, Akira MINO, Jun MURAKAMI
  • Publication number: 20140067210
    Abstract: When a MODE selector SW is manipulated while CVT automatic shifting mode is selected, the shifting mode is switched to STEP-AT automatic shifting mode. Then, when the shift lever of a shifting device is manipulated by the driver while the CVT automatic shifting mode is selected as the shifting mode of a CVT, the then-set automatic shifting control mode for the CVT is maintained whereas the shifting mode of the CVT is switched to sport mode. When the sport mode being selected as the shifting mode of the CVT is canceled, the shifting mode of the CVT is switched to the mode selected before the switchover to the sport mode, that is, the maintained automatic shifting control mode, unless the MODE selector SW is manipulated during execution of the sport mode.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 6, 2014
    Applicants: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA, MITSUBISHI JIDOSHA ENGINEERING KABUSHIKI KAISHA
    Inventors: Akira MINO, Seiichi INUKAI
  • Publication number: 20120241978
    Abstract: A semiconductor device including a first insulating film formed above a semiconductor substrate and having a first relative dielectric constant; a second insulating film formed above the first insulating film and having a second relative dielectric constant greater than the first relative dielectric constant; a plurality of columnar plugs extending longitudinally through the first and the second insulating films having a first sidewall extending through the first insulating film and a second sidewall extending through the second insulating film, wherein the second sidewall is tapered; a third insulating film formed above the second insulating film and having a third relative dielectric constant less than the second relative dielectric constant of the second insulating film; trenches extending through the third insulating film and reaching an upper portion of the plugs; and an interconnect wiring comprising metal formed within the trenches and contacting the upper portion of the plugs.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Akira MINO