Patents by Inventor Akira Mitsuiki

Akira Mitsuiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10078182
    Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 18, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shinichi Watanuki, Akira Mitsuiki, Atsuro Inada, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 9589954
    Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Tomoo Nakayama, Shigeaki Shimizu, Hiroyuki Okuaki
  • Publication number: 20160247931
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, a silicon film, for the memory gate electrode of a memory cell in a nonvolatile memory is formed via an insulating film so as to cover the control gate electrode of the memory cell. After the silicon film and the insulating film are removed from a peripheral circuit region, a silicon film for the gate electrode of a MISFET is formed over the silicon film over a memory cell region of the semiconductor substrate and over the peripheral circuit region thereof. After the silicon film is patterned to form a gate electrode over the peripheral circuit region, the insulating film is removed from the memory cell region. Then, over the silicon film over the memory cell region, an oxide film is formed. Subsequently, the oxide film, and, the silicon film over the silicon film over the memory cell region are etched back to form the memory gate electrode adjacent to the control gate electrode via the insulating film.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 25, 2016
    Applicant: Renesas Electronics Corporation
    Inventor: Akira MITSUIKI
  • Publication number: 20160056233
    Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 25, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira MITSUIKI, Tomoo NAKAYAMA, Shigeaki SHIMIZU, Hiroyuki OKUAKI
  • Patent number: 8492227
    Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Atsuro Inada
  • Publication number: 20110053367
    Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.
    Type: Application
    Filed: July 16, 2010
    Publication date: March 3, 2011
    Inventors: Akira MITSUIKI, Atsuro Inada
  • Patent number: 7510981
    Abstract: A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride film and a protective film which covers the silicon nitride film, on a semiconductor substrate; selectively etching the semiconductor substrate using the protective film as a mask to form a trenched portion; removing the protective film to expose the silicon nitride film; depositing an element isolation film, so as to fill the trenched portion therewith and cover the silicon nitride film; removing the element isolation film formed on the silicon nitride film by polishing thereof until the silicon nitride film is exposed; and removing the silicon nitride film.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 31, 2009
    Assignee: NEC Electronics Corporations
    Inventors: Akira Mitsuiki, Tomoo Nakayama, Osamu Fujita
  • Patent number: 7462566
    Abstract: In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film through a fine-pattern-forming resist film while using the second film as an etching stopper (S102), and the fine-pattern-forming resist film is removed (S104). Subsequently, light exposure is carried out using a resist film (S106 to S110), and the second film, the first film and the process target film are then selectively dry-etched in a sequential manner, to thereby form the process target film into a predetermined pattern (S112). The first film remained on the process target film is then removed (S114).
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: December 9, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Masato Fujita, Kensuke Taniguchi, Akira Mitsuiki
  • Publication number: 20080194107
    Abstract: The present invention aims to improve the controllability of dimensions at the time when a silicon substrate or a film formed on top of the silicon substrate is etched. For this purpose, a SiN film is formed so as to be in contact with the top of an element-forming surface of a silicon substrate, and the SiN film is selectively removed to form an opening portion. Then, a plasma processing is carried out on the element-forming surface of the silicon substrate to remove deposits attached on sidewalls of the opening portion formed in the SiN film. After that, the silicon substrate is selectively removed by using the SiN film as a mask to form a concave portion in the silicon substrate.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 14, 2008
    Applicant: NEC Electronics Corporation
    Inventors: Akira Mitsuiki, Atsuro Inada
  • Publication number: 20080085608
    Abstract: In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film through a fine-pattern-forming resist film while using the second film as an etching stopper (S102), and the fine-pattern-forming resist film is removed (S104). Subsequently, light exposure is carried out using a resist film (S106 to S110), and the second film, the first film and the process target film are then selectively dry-etched in a sequential manner, to thereby form the process target film into a predetermined pattern (S112). The first film remained on the process target film is then removed (S114).
    Type: Application
    Filed: November 16, 2006
    Publication date: April 10, 2008
    Inventors: Masato Fujita, Kensuke Taniguchi, Akira Mitsuiki
  • Publication number: 20070087520
    Abstract: A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride film and a protective film which covers the silicon nitride film, on a semiconductor substrate; selectively etching the semiconductor substrate using the protective film as a mask to form a trenched portion; removing the protective film to expose the silicon nitride film; depositing an element isolation film, so as to fill the trenched portion therewith and cover the silicon nitride film; removing the element isolation film formed on the silicon nitride film by polishing thereof until the silicon nitride film is exposed; and removing the silicon nitride film.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 19, 2007
    Applicant: NEC Electronics Corporation
    Inventors: Akira Mitsuiki, Tomoo Nakayama, Osamu Fujita
  • Patent number: 6716761
    Abstract: A resist pattern is formed on a film to be processed using a lithography technique. The line width of the resist pattern is narrowed using a slimming technique. Thereafter, the pattern of a first film to be processed is formed in the space that has been widened by slimming, utilizing the phenomenon in which anisotropic etching under a reduced pressure accelerates the etching rate in the vicinity of the side of the line of the pattern compared to other areas. An underlying second film to be processed is etched using the first film to be processed as a mask. Thereby the pattern of the second film to be processed that has a pitch ½ the lithography pattern is formed.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: April 6, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Akira Mitsuiki
  • Publication number: 20020094688
    Abstract: A resist pattern is formed on a film to be processed using a lithography technique. The line width of the resist pattern is narrowed using a slimming technique. Thereafter, the pattern of a first film to be processed is formed in the space that has been widened by slimming, utilizing the phenomenon in which anisotropic etching under a reduced pressure accelerates the etching rate in the vicinity of the side of the line of the pattern compared to other areas. An underlying second film to be processed is etched using the first film to be processed as a mask. Thereby the pattern of the second film to be processed that has a pitch ½ the lithography pattern is formed.
    Type: Application
    Filed: December 21, 2001
    Publication date: July 18, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Akira Mitsuiki
  • Patent number: 6376383
    Abstract: A gate oxide film and a polysilicon layer are formed on a silicon substrate, and a pattern of photoresist is formed on the polysilicon layer. A silicon layer is etched halfway using a CF type gas such as CF4, CHF3, CH2F2 and C4F8 or a mixed gas including the same with the photoresist serving as a mask. This leaves fluorocarbon type deposition on sides of the etched hole. Then, any residue of the silicon film is etched using the gas of Cl2, HBr, SF6 or O2. This makes it possible to provide a configuration having inclined sides after etching.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: April 23, 2002
    Assignee: NEC Corporation
    Inventor: Akira Mitsuiki
  • Patent number: 6372602
    Abstract: The present invention provides a method of forming a shallow trench isolation structure in a substrate. The method comprises the steps of: forming an isolation silicon oxide film which comprises an upper portion extending over a silicon oxide film over a silicon nitride film and a lower portion extending in a trench in a silicon substrate; and carrying out an isotropic etching to said upper portion of said isolation silicon oxide film and said silicon oxide film, thereby forming an isolation trench structure without divots in said trench in said silicon substrate.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventor: Akira Mitsuiki
  • Publication number: 20010001732
    Abstract: A photo-resist etching mask is formed on a silicon oxide layer deposited on a polysilicon layer, and the silicon oxide and the polysilicon are respectively etched by using gaseous etchant containing CF4 and another gaseous etchant containing HBr and O2, wherein etching residue of fluorocarbon and a surface portion of the polysilicon layer are etched away by using Cl2 gas so as to pattern the polysilicon without undesirable influence of the etching residue.
    Type: Application
    Filed: May 6, 1999
    Publication date: May 24, 2001
    Inventor: AKIRA MITSUIKI
  • Patent number: 6200902
    Abstract: In the process of simultaneously etching a polysilicon layer in a groove of a memory cell section and a polysilicon layer in a peripheral circuit section, a Cl2/HBr-based gas is used as a first etching step, and this etching is performed until polysilicon in the peripheral section is removed. Next, the gas is switched to a C12/HBr/O2-based gas to remove an etched particulate resist film having accumulated in the groove. As a final step, the polysilicon layer remaining in the groove is etched with a HBr/O2-based gas having a high selectivity ratio against an oxide film.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: March 13, 2001
    Assignee: NEC Corporation
    Inventor: Akira Mitsuiki