Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in parallel in a predetermined direction, wherein each of the power units includes a plurality of semiconductor elements placed on a metal plate having predetermined gaps with each other. The semiconductor elements of each of the two power units include a near-sided semiconductor element that is closer to an inlet of the resin among the two semiconductor elements having the predetermined gap therebetween. A structure is positioned on a passage and downstream in a resin flow direction relative to a predetermined position that corresponds to end parts of the near-sided semiconductor elements. The structure is a joint to connect the two power units placed adjacent to each other in the predetermined direction, and to be integrally sealed with the resin, along with the power unit.

Abstract: A semiconductor module includes a semiconductor device and a flexible relay member. The semiconductor device includes a resin member, an electronic component sealed with the resin member, and a lead member having an inner lead and an outer lead. The inner lead is located inside the resin member and electrically connected to the electronic component. The outer lead extends from the inner lead and is located outside the resin member. The relay member is electrically connected to the outer lead to electrically connect the electronic component to a connection target to be electrically connected to the semiconductor device.

Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in parallel in a predetermined direction, wherein each of the power units includes a plurality of semiconductor elements placed on a metal plate having predetermined gaps with each other. The semiconductor elements of each of the two power units include a near-sided semiconductor element that is closer to an inlet of the resin among the two semiconductor elements having the predetermined gap therebetween. A structure is positioned on a passage and downstream in a resin flow direction relative to a predetermined position that corresponds to end parts of the near-sided semiconductor elements. The structure is a joint to connect the two power units placed adjacent to each other in the predetermined direction, and to be integrally sealed with the resin, along with the power unit.

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract: A printed wiring board includes a main body having a mounting portion and ground and power supply pads in the mounting portion such that a ground line of a semiconductor device is connected to a ground pad and a power supply line of the device is connected to a power supply pad, and a layered capacitor disposed in the main body and having a high dielectric constant layer and first and second layer electrodes sandwiching the dielectric layer. One of the electrodes is connected to the power supply line and the other electrode is connected to the ground line, the first electrode has a solid pattern including passage holes through which second rod terminals connected to the second electrode pass in a non-contacting manner, and the second electrode has a solid pattern including passage holes through which first rod terminals connected to the first electrode pass in a non-contacting manner.

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic.

Abstract: A printed wiring board including a first insulating layer, a second insulating layer formed over the first insulating layer, a capacitor portion including an upper electrode, a lower electrode and a ceramic high dielectric layer formed between the upper electrode and the lower electrode, the capacitor portion sandwiched by the first insulating layer and the second insulating layer, an upper electrode connecting portion passing through the capacitor portion without contact and through the second insulating layer and electrically connected to the upper electrode of the capacitor portion, and a lower electrode connecting portion passing through the second insulating layer and the upper electrode of the capacitor portion without contact and electrically connected to the lower electrode in contact.

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic.

Abstract: A printed wiring board includes a main body having a mounting portion and ground and power supply pads in the mounting portion such that a ground line of a semiconductor device is connected to a ground pad and a power supply line of the device is connected to a power supply pad, and a layered capacitor disposed in the main body and having a high dielectric constant layer and first and second layer electrodes sandwiching the dielectric layer. One of the electrodes is connected to the power supply line and the other electrode is connected to the ground line, the first electrode has a solid pattern including passage holes through which second rod terminals connected to the second electrode pass in a non-contacting manner, and the second electrode has a solid pattern including passage holes through which first rod terminals connected to the first electrode pass in a non-contacting manner.

Abstract: A method of manufacturing a printed wiring board including preparing a high-dielectric capacitor sheet including a ceramic high-dielectric layer sandwiched by upper and lower electrode sheets, attaching the high-dielectric capacitor sheet to a first insulating layer, forming through holes for the upper and lower electrode sheets such that the through holes penetrate through the ceramic high-dielectric layer and upper and lower electrode sheets, forming a second insulating layer which fills the through holes and covers an upper surface of the high-dielectric capacitor sheet, forming an upper electrode connecting first hole, an upper electrode connecting second hole and a lower electrode connecting hole, filling the upper holes with conductive material such that the upper electrode connecting first hole and the upper electrode connecting second hole are connected to form an upper electrode connection portion, and filling the lower electrode connecting hole with conductive material to form a lower electrode conn

Abstract: A printed wiring board including a first insulating layer, a second insulating layer formed over the first insulating layer, a capacitor portion including an upper electrode, a lower electrode and a ceramic high dielectric layer formed between the upper electrode and the lower electrode, the capacitor portion sandwiched by the first insulating layer and the second insulating layer, an upper electrode connecting portion passing through the capacitor portion without contact and through the second insulating layer and electrically connected to the upper electrode of the capacitor portion, and a lower electrode connecting portion passing through the second insulating layer and the upper electrode of the capacitor portion without contact and electrically connected to the lower electrode in contact.

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic.

Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41.

Abstract: A semiconductor device is disclosed that includes a first and a second semiconductor package. Each semiconductor package includes a semiconductor element, a plurality of electrode members, and an encapsulating member. The semiconductor elements are interposed between the respective electrode members, and the electrode members are in electrical communication with and provide heat transfer for the respective semiconductor element. The encapsulating member encapsulates the respective semiconductor element between the respective electrode members, and an outer surface of each of the electrode members is exposed from the respective encapsulating member. Each semiconductor package includes a connecting terminal electrically coupled to one of the electrode members and extending outward so as to be exposed from the respective encapsulating member. The connecting terminals are electrically connected by abutment or via a conductive junction material.

Abstract: A semiconductor device includes: first and second metal electrodes having inner surfaces facing each other; a semiconductor element sandwiched between the electrodes; and first and second insulation substrates disposed on the electrode and opposite to the semiconductor element, respectively. Each of the insulation substrates is made of ceramics. At least one of the electrodes includes a plurality of layers stacked in a direction parallel to a stacking direction. One layer disposed on a semiconductor element side has a thermal expansion coefficient, which is higher than that of another layer disposed on an insulation substrate side.

Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41.

Abstract: A semiconductor device includes: first and second metal electrodes having inner surfaces facing each other; a semiconductor element sandwiched between the electrodes; and first and second insulation substrates disposed on the electrode and opposite to the semiconductor element, respectively. Each of the insulation substrates is made of ceramics. At least one of the electrodes includes a plurality of layers stacked in a direction parallel to a stacking direction. One layer disposed on a semiconductor element side has a thermal expansion coefficient, which is higher than that of another layer disposed on an insulation substrate side.

Abstract: A technique for distributed printing that ensures favorable operability within a sufficiently short time. The procedure first generates intermediate print data and executes the parallel rendering process by time sharing to sequentially convert page data on the first page of the intermediate print data into data adequate for the printers. Transmission of final print data converted for the first printer is carried out in parallel with the rendering process for the second printer. In a similar manner, transmission of converted final print data to the second printer and third printers is carried out in parallel with the rendering process for the next printer. The parallel rendering process sequentially converts page data on the second page of the intermediate print data into data adequate for the printers. Subsequently, the parallel rendering process sequentially converts page data on the third page of the intermediate print data into data adequate for the printers.

Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41.