Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: Checking efficiency of property checking is improved. The operation synthesis tool synthesizes an RTL circuit description from a behavioral level circuit description. In addition, the property generating unit generates a behavioral level property from the behavioral level circuit description. Subsequently, the property converting unit converts the generated behavioral level property into an RTL property. The model checking unit then checks the RTL circuit description by model checking technique using the RTL property.

Abstract: Checking efficiency of property checking is improved. The operation synthesis tool synthesizes an RTL circuit description from a behavioral level circuit description. In addition, the property generating unit generates a behavioral level property from the behavioral level circuit description. Subsequently, the property converting unit converts the generated behavioral level property into an RTL property. The model checking unit then checks the RTL circuit description by model checking technique using the RTL property.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: A validation processing apparatus is to be provided, which allows a user to easily check whether a request designated by the user is satisfied by a data processing system, which is the object to be validated, and to easily check a result of coverage measurement in the data processing system based on a coverage metrics designated by the user. The validation processing apparatus acquires a state transition graph of the data processing system, being the object to be validated; acquires the request to the data processing system; and acquires a coverage metrics indicating events to be included in the validation range of the data processing system. Then the validation processing apparatus validates whether the acquired state transition graph satisfies the request; measures the coverage in the state transition graph according to the acquired coverage metrics; and outputs a result.

Abstract: A complete procedure for verifying register-transfer logic against its scheduled behavior in a high-level synthesis environment is provided. A new method that is both complete and practical for verification is provided. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high-level synthesis--performed manually or by means of high-level synthesis software--proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. Equivalence checking task is partitioned into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RYL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, irrelevant portions of the design are automatically abstracted out, significantly simplifying the task that must be performed by a back-end model checker.