Patents by Inventor Akira Muramatsu

Akira Muramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020056298
    Abstract: A vehicle door lock apparatus includes a lever mechanism directly connected with a key cylinder provided at the outside door handle for locking and unlocking the vehicle door in response to rotation operation of the key cylinder. The lever mechanism is provided with a key rotor directly connected with the key cylinder, and a key lever directly connected with the key rotor. An input shaft of the lever mechanism formed by the key rotor is inclinable relative to an output shaft of the lever mechanism formed by the key lever, and this inclination is absorbed through the connection between the key rotor and the key lever.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 16, 2002
    Inventors: Katsutoshi Fukunaga, Makoto Suzumura, Ryujiro Akizuki, Norio Konomoto, Akira Muramatsu, Shigeru Hayakawa, Yasuhiko Sono
  • Publication number: 20020056996
    Abstract: A vehicle door lock apparatus includes a first body and a second body integrated so as to be adapted to be integrally assembled to the door. The vehicle door lock apparatus further includes guide projections formed at one of the first and second bodies, and guide grooves formed at the other of the first and second bodies. In addition, a stopper is provided for preventing the separation of integrated first and second bodies by the engagement between the guide projections and the guide grooves.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 16, 2002
    Inventors: Katsutoshi Fukunaga, Makoto Suzumura, Ryujiro Akizuki, Norio Konomoto, Akira Muramatsu, Shigeru Hayakawa, Yasuhiko Sono
  • Patent number: 6321213
    Abstract: An electronic money storage apparatus includes that an amount of remittance p is determined on a remitting side and a receiving side. A remitting apparatus obtains a remitter's transaction fee x and an amount y to be stored in a transaction fee storage area. The remitting apparatus obtains a sum of p and x, i.e., p+x from an electronic money storage area, divides the sum into an amount y to be stored on the remitting side and an amount remained p+x−y, stores y in a transaction fee storage area, and sends p+x −y to the receiving side.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: November 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ito, Masaaki Hiroya, Takeshi Teramura, Akira Muramatsu, Yoshiaki Kawatsura
  • Publication number: 20010038211
    Abstract: A door lock system for a vehicle includes a latch mechanism, a link mechanism and a housing. The latch mechanism is adapted to a vehicle door and latches the vehicle door to a vehicle body. The link mechanism includes an electric driving source and a plurality of lever members for selectively locking and unlocking the latch mechanism. The housing accommodates the latch mechanism and the link mechanism.
    Type: Application
    Filed: March 16, 2001
    Publication date: November 8, 2001
    Inventors: Shigeru Hayakawa, Hiroshi Ban, Norio Konomoto, Katsutoshi Fukunaga, Makoto Suzumura, Akira Muramatsu, Yasuhiko Sono
  • Publication number: 20010035653
    Abstract: A door lock system for a vehicle includes a) a latch mechanism which is adapted to a vehicle door and which holds the vehicle door to a vehicle body, b) an open link which is engagable and disengagable with the latch mechanism, c) a swing lever which is connected to the open link, d) an electric driving source having a gear member, and e) a rotary gear member which is arranged between the swing lever and the electric driving source so as to be meshed with the gear member of the electric driving source. The rotary gear member is directly and engagably connected to the swing lever.
    Type: Application
    Filed: March 16, 2001
    Publication date: November 1, 2001
    Inventors: Shigeru Hayakawa, Hiroshi Ban, Norio Konomoto, Katsutoshi Fukunaga, Makoto Suzumura, Akira Muramatsu, Yasuhiko Sono
  • Publication number: 20010033082
    Abstract: A door lock system for a vehicle includes a latch mechanism, an open link, an inside lever and a cancel lever. The latch mechanism is adapted to a vehicle door and latches the vehicle door to a vehicle body. The open link is engagable and disengagable with the latch mechanism. The inside lever is adapted to an inside handle of the vehicle door and is engagable with the open link. The cancel lever is connected to the open link and is arranged between the inside lever and the open link so as to be engagable with the inside lever when the open link is disengaged from the latch mechanism.
    Type: Application
    Filed: March 16, 2001
    Publication date: October 25, 2001
    Inventors: Shigeru Hayakawa, Hiroshi Ban, Norio Konomoto, Katsutoshi Fukunaga, Makoto Suzumura, Akira Muramatsu, Yasuhiko Sono
  • Patent number: 6241293
    Abstract: A door lock device includes a base plate 2 having horizontal wall 21 connected to a door lock body 31 and vertical wall 22 perpendicular to the horizontal wall 21, a rotation lever 49 rotatably supported to the vertical wall 22, a key lever 47 rotatably supported to a housing 64 of an actuator 6 which is secured to the vertical wall 22, and a connecting lever 48 having one end and the other end, one end being coupled to the rotation lever 49 after rotation of one end to the rotation lever 49, the other being coupled to the key lever 47 after rotation of the other end to the key lever 47, the connecting lever 48 being in parallel and close to the connecting vertical wall 22 of the base plate 2.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: June 5, 2001
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Shigeru Hayakawa, Norio Konomoto, Akira Muramatsu
  • Patent number: 5867679
    Abstract: A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
    Type: Grant
    Filed: January 30, 1991
    Date of Patent: February 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Teruo Tanaka, Naoki Hamanaka, Koichiro Omoda, Shigeo Nagashima, Akira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Junji Nakagoshi, Kazuo Ojima
  • Patent number: 5691403
    Abstract: Disclosed is biodegradable compositions comprising a biodegradable resin and starch, wherein fat or oil treated starch or its gelatinized product is utilized as the starch and thereby its production cost and biodegradability is improved without losing its mechanical properties. Biodegradable compositions comprising a gelatinized product of fat or oil treated starch and a biodegradable resin. A process for the production of the biodegradable composition comprising a gelatinized fat or oil treated starch and a biodegradable resin described above, which comprises heating and kneading fat or oil treated starch and a biodegradable resin in the presence of water or water and a plasticizer.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: November 25, 1997
    Assignee: Nihon Shokuhin Kako Co., Ltd.
    Inventors: Tetsuya Shitaohzono, Akira Muramatsu, Jiro Hino
  • Patent number: 5517619
    Abstract: In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: May 14, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Akira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Takehisa Hayashi, Teruo Tanaka, Shigeo Nagashima
  • Patent number: 5471204
    Abstract: In a radio communication apparatus for use in carrying out a receiving operation of selectively receiving a call signal specific to the apparatus, a counter is counted up one by one to produce a count each time when the call signal is received. The count is successively compared with a plurality of threshold values by a control section to determine a controllable perceptual notifying mode which may be at least one of an audible and a visual notifying modes. In the audible notifying mode, the control section varies a volume of an audible tone through a tone generator in dependency upon the count. In the visual notifying mode, display elements, such as light emitting diodes, provide visual displays which are different from one another and which are determined by the count. Such variations of the audible tone and/or the visual displays are helpful for notifying a possessor of reception of the call signal.
    Type: Grant
    Filed: January 10, 1994
    Date of Patent: November 28, 1995
    Assignee: NEC Corporation
    Inventors: Kazuhiro Kudoh, Akira Muramatsu, Tetsumi Ishiguro
  • Patent number: 5339396
    Abstract: In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: August 16, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Akira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Takehisa Hayashi, Teruo Tanaka, Shigeo Nagashima
  • Patent number: 5283568
    Abstract: A radio pager having means for automatically adjusting the rising time of a high-speed clock. The pager includes a plurality of circuit elements for adjusting the rising time of the high-speed clock, i.e., for compensating the degree of stability of a high-speed clock generating circuit. On the start of a low-speed clock, the high-speed clock generating circuit sequentially selects and connects the circuit elements to thereby count the resulting rising times of the high-speed clock. One of the circuit elements having resulted the shortest rising time is written to a storage. When the high-speed clock is needed, e.g., when a message should be displayed, the stored circuit element is connected to the high-speed clock generating circuit.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: February 1, 1994
    Assignee: NEC Corporation
    Inventors: Takayuki Asai, Akira Muramatsu
  • Patent number: 5129093
    Abstract: A parallel computer has an operation request function and a plurality of processor elements. Each processor element has a sharable distributed memory for holding data, and is interconnected to a network to permit communication. Each processor element comprises a request sent unit for sending an operation request message for causing another processor element connected to a memory module to execute a recursive defining operation. The memory module stores data to be recursively defined. Each processor element further comprises an operation request execution element for accepting a message from another processor, temporarily stopping any other operation of the processor element in accordance with the content of the message, and executing the requested operation. Registers are also used for executing the operation requested by the other processor in addition to the general purpose registers and floating point registers.
    Type: Grant
    Filed: November 17, 1988
    Date of Patent: July 7, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Akira Muramatsu, Ikuo Yoshihara, Kazuo Nakao
  • Patent number: 5043873
    Abstract: A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data.
    Type: Grant
    Filed: August 17, 1989
    Date of Patent: August 27, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Akira Muramatsu, Kousuke Sakoda, Ikuo Yoshihara, Kazuo Nakao, Makoto Nohmi, Naoki Hamanaka, Shigeo Nagashima, Teruo Tanaka
  • Patent number: 4982361
    Abstract: The present invention is capable of registering and reading out a logical element for which the state of the output pin changes. The system includes an input side reading out circuit for reading out the kind of logical element and the states of all the input pins thereof, a decision circuit for deciding the presence of the output pin that the status change is produced on when a logical operation is carried out according to the kind of logical element, an output side reading out circuit for reading out the information related to the logical element of the output pin producing the status change, and an exchange sending circuit for sending each information read out from the output side reading out circuit to the desired registering and reading out circuit for precise high speed logic simulation of a large scale logic circuit containing MOS-type logical elements.
    Type: Grant
    Filed: October 21, 1985
    Date of Patent: January 1, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Miyaoka, Akira Muramatsu, Motohisa Funabashi
  • Patent number: 4951193
    Abstract: In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
    Type: Grant
    Filed: August 14, 1987
    Date of Patent: August 21, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Akira Muramatsu, Kousuke Sakoda, Ikuo Yoshihara, Kazuo Nakao, Makoto Nohmi, Naoki Hamanaka, Shigeo Nagashima, Teruo Tanaka
  • Patent number: 4899213
    Abstract: A system is provided for producing image signals of a photographed subject image by a solid state image sensing device and for producing a brightness signal and line sequential color difference signals from the image signal. The subject image is sensed by the image sensing device which has a color filter formed thereon. First and second horizontal scanning lines of picture elements are alternately arranged and the picture elements are opposed to filter elements of the color filter. The first horizontal scanning lines separately transmit at least red light and green light and the second horizontal scanning lines transmit at least blue light and green light, to thereby obtain color image signals. The image signal thus obtained are signal processed to produce the line sequential color difference signals R-Y and B-Y. With this signal processing, the system can produce the image signals including the line sequential color difference signals by a simplified arrangement without impairing the color productivity.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: February 6, 1990
    Inventors: Masahiro Konishi, Masafumi Inuiya, Akira Muramatsu, Masahiro Kato
  • Patent number: 4876591
    Abstract: A video signal generating device with which a video signal of high resolution is produced while significantly suppressing the generation of color Moire disturbance. The received optical image is split into two beams and applied to respective color and monochrome image sensors. The optical beam applied to the color sensor is optically filtered to limit it in spatial frequency to a band below that applied to the monochrome sensor. A high frequency luminance signal is produced from an output of the monochrome sensor, a low frequency luminance signal is produced from the output of the color sensor, and a composite luminance signal is formed from the combination of the high and low frequency luminance signals. The overall resolution of the device is determined by the monochrome signals produced by the monochrome sensor.
    Type: Grant
    Filed: February 13, 1989
    Date of Patent: October 24, 1989
    Assignee: Fuji Photo Film Co.
    Inventor: Akira Muramatsu
  • Patent number: 4838226
    Abstract: An apparatus for controlling intake air flow rate in an internal combustion engine comprises a throttle valve disposed in intake air passage for swing movement to change a flow rate of air to be supplied to combustion chambers of the engine, a stopper portion to which the throttle valve is abutted so as to stop swinging thereof in a full closed portion thereof, a spring for continually urging the throttle valve towards the full closed position, a control unit for determining a desired opening degree of the throttle valve in accordance with requirements on the engine, an actuator for generating a driving force for swinging the throttle valve to the desired opening degree in accordance with a command signal from the control unit, and geared mechanism for transmitting the driving force from the actuator to the throttle valve. The geared mechanism includes a pair of gears, each having a gear tooth portion. The gears are able to engage with each other exclusively at such gear tooth portions.
    Type: Grant
    Filed: May 6, 1988
    Date of Patent: June 13, 1989
    Assignee: Nippondenso Co., Ltd.
    Inventors: Toshio Matsuzawa, Kazuji Minagawa, Akira Muramatsu, Tomoaki Abe, Masashi Kiyono, Shigeru Kamio, Katsuya Maeda, Mitsunori Takao