Abstract: A method is provided for testing a processor of an information processing apparatus that includes a cache memory, a first memory, and a second memory. Backups of a first instruction sequence and first data that, when a modification is made thereto, is incapable of being recovered using an instruction sequence held in the first memory are made in the second memory, the second memory being not accessed by the cache memory. In causing the processor to execute the instruction sequence, a second instruction sequence and second data that is fetched and put in the cache memory is modified. While the processor is executing the instruction sequence, when an error occurs due to a modification in a third instruction sequence that is incapable of being recovered using the instruction sequence, the first instruction sequence in the second memory is written to the first memory.

Abstract: A relay device for relaying transfer data to be transmitted between the devices has a plurality of testers. Each of the testers determines whether received transfer data is normal or not, and discards the transfer data that is determined abnormal. The relay device also has a counter that counts a number of transfer data discarded by each of the testers respectively, and a determiner that determines whether an operation of each tester is normal or not based on the number of discarded transfer data counted by the counter.

Abstract: A relay device for relaying transfer data to be transmitted between the devices has a plurality of testers. Each of the testers determines whether received transfer data is normal or not, and discards the transfer data that is determined abnormal. The relay device also has a counter that counts a number of transfer data discarded by each of the testers respectively, and a determiner that determines whether an operation of each tester is normal or not based on the number of discarded transfer data counted by the counter.