Patents by Inventor Akira Nishimoto

Akira Nishimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060224784
    Abstract: The transfer rates of streams are assured if the plural streams are mixed. A disk array system required to process multiple streams from a host computer carries out recognition of the transfer rates, recognition of drive performance and a fault processing time, determines the size of a sequential buffer holding each stream, and determines the drive I/O size. Using the transfer rate and buffer size determined in these processing steps, required end times at which prefetch and destage should be terminated are found. Based on the times, the I/O priorities are determined.
    Type: Application
    Filed: June 6, 2005
    Publication date: October 5, 2006
    Inventors: Akira Nishimoto, Naoto Matsunami
  • Publication number: 20060217495
    Abstract: A polyester resin composition for profile extrusion molding comprising an amorphous polyester, at least one component selected from the group consisting of a crystalline polyester and a nucleating agent, and optionally a reactive compound; a polyester resin composition for profile extrusion molding comprising a polyester resin, and a reactive compound having a weight average molecular weight of 200 to 500,000; and a profile shape comprising a resin having a reduced viscosity ratio of 1.01 to 3.00, a reduced viscosity ratio being a ratio of a reduced viscosity of a resin after molding to that of a resin before molding. They do not suffer from sagging in the molding process, they improve the shape accuracy at corners and edges of profile shapes from a die to a sizing step and also resistance to whitening on bending in transparent products, and can provide profile shapes having good solvent resistance and detergent resistance.
    Type: Application
    Filed: June 6, 2006
    Publication date: September 28, 2006
    Inventors: Kenji Shiga, Akira Nishimoto, Osamu Iritani, Kazunori Komatsu, Mitsuo Nishida
  • Patent number: 7084214
    Abstract: A polyester resin composition for profile extrusion molding comprising an amorphous polyester, at least one component selected from the group consisting of a crystalline polyester and a nucleating agent, and optionally a reactive compound; a polyester resin composition for profile extrusion molding comprising a polyester resin, and a reactive compound having a weight average molecular weight of 200 to 500,000; and a profile shape comprising a resin having a reduced viscosity ratio of 1.01 to 3.00, a reduced viscosity ratio being a ratio of a reduced viscosity of a resin after molding to that of a resin before molding. They do not suffer from sagging in the molding process, they improve the shape accuracy at corners and edges of profile shapes from a die to a sizing step and also resistance to whitening on bending in transparent products, and can provide profile shapes having good solvent resistance and detergent resistance.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: August 1, 2006
    Assignee: Toyo Boseki Kabushiki Kaisha
    Inventors: Kenji Shiga, Akira Nishimoto, Osamu Iritani, Kazunori Komatsu, Mitsuo Nishida
  • Patent number: 7043602
    Abstract: A diskarray system includes a disk device for storing write data received from a computer, a cache memory, and a controller for controlling input and output of data to and from the disk device. The controller determines whether or not the write data is already written in a storage area of the diskarray system to be written specified by a write command received from the computer. When the write data for the storage area to be written is not written yet in the diskarray system, the controller receives the write data according to the write command and stores the received data in the cache memory.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: May 9, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Akira Nishimoto, Naoto Matsunami, Ikuya Yagisawa
  • Patent number: 7024522
    Abstract: To provide a disk array system which particularly enables the use of a WORM function when the disk array system uses RAID. When receiving a write request from a computer (100), it is judged whether or not a writing of write data from the computer is possible, based on a content indicated by write inhibition information. If the writing is possible, the guarantee code of the transferred data is generated, the write inhibition information indicating that a region in which the data is stored is not writable is generated, and the generated write inhibition information is stored in the guarantee code, the guarantee code storing the write inhibition information is assigned to the region in which the data received from the computer (100) is stored, and the data to which the guarantee code storing the write inhibition information is assigned is stored in a cache memory (230) and/or a disk drive (270). If the write data from the computer (100) is not writable, it is informed to the computer (100).
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: April 4, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Mannen, Naoto Matsunami, Akira Nishimoto, Yusuke Nonaka
  • Publication number: 20060069868
    Abstract: A hybrid-type storage system having both SAN and NAS interfaces can be implemented by simple hardware capable of carrying out a SAN function independently of a NAS function and a NAS load. To be more specific, a controller of the storage system comprises a NAS controller for accepting an I/O command issued for a file unit and a SAN controller for accepting an I/O command issued for a block unit. The NAS controller converts an I/O command issued for a file unit into an I/O command issued for a block unit, and transfers the I/O command issued for a block unit to the SAN controller. The SAN controller makes an access to data stored in a disk apparatus in accordance with an I/O command received from the SAN or from the NAS controller as a command issued for a block unit. The NAS and SAN controllers are capable of operating independently of each other.
    Type: Application
    Filed: November 15, 2005
    Publication date: March 30, 2006
    Inventors: Yusuke Nonaka, Naoto Matsunami, Ikuya Yagisawa, Akira Nishimoto
  • Publication number: 20060047872
    Abstract: A storage technology for improving reliability in writing host data to a storage device is provided. A first check code based on write data is stored in cache memory 370, and storage section 50 is instructed to write, in specified predetermined storage area, write data with the first check code appended thereto, after which the storage section 50 is instructed to read data stored in said predetermined storage area; a second check code is generated on the basis of the read data, and in the event that the correspondence relationship between the first and second check codes is correct, it is decided that the write data was written normally to the storage section 50.
    Type: Application
    Filed: October 26, 2004
    Publication date: March 2, 2006
    Inventors: Yutaka Nakagawa, Ikuya Yagisawa, Akira Nishimoto
  • Publication number: 20060031651
    Abstract: The storage system is coupled to a computer, and includes a controller and a disk drive including a plurality of logical volumes, at least in one of which updating prohibition information indicating inclusion of an area assigned an updating prohibition attribute is recorded. The controller includes a configuration management module that sets the logical volume assigned the updating prohibition attribute as a logical volume of a migration source, another logical volume as a logical volume of a migration destination, and the updating prohibition information concerning the logical volume of the migration source in the logical volume of the migration destination, and a migration module that copies data of the logical volume of the migration source to the logical volume of the migration destination after the setting of the updating prohibition information concerning the logical volume of the migration source in the logical volume of the migration destination.
    Type: Application
    Filed: October 8, 2004
    Publication date: February 9, 2006
    Inventors: Yusuke Nonaka, Naoto Matsunami, Akira Nishimoto, Yutaka Nakagawa
  • Publication number: 20060026345
    Abstract: To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.
    Type: Application
    Filed: October 8, 2004
    Publication date: February 2, 2006
    Inventors: Akira Nishimoto, Naoto Matsunami, Masahiko Sato, Hidemi Baba
  • Patent number: 6981094
    Abstract: A hybrid-type storage system having both SAN and NAS interfaces can be implemented by simple hardware capable of carrying out a SAN function independently of a NAS function and a NAS load. To be more specific, a controller of the storage system comprises a NAS controller for accepting an I/O command issued for a file unit and a SAN controller for accepting an I/O command issued for a block unit. The NAS controller converts an I/O command issued for a file unit into an I/O command issued for a block unit, and transfers the I/O command issued for a block unit to the SAN controller. The SAN controller makes an access to data stored in a disk apparatus in accordance with an I/O command received from the SAN or from the NAS controller as a command issued for a block unit. The NAS and SAN controllers are capable of operating independently of each other.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: December 27, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Nonaka, Naoto Matsunami, Ikuya Yagisawa, Akira Nishimoto
  • Publication number: 20050268055
    Abstract: In the case in which data in a storage system A is remotely copied to a storage system B, it is not taken into account whether the data of the remote copy is WORM data. In the case in which a setting is made such that data stored in a volume in the storage system A is copied to a volume in the storage system B, storage system A judges whether an attribute to the effect that data can be referred to and can be updated or to the effect that data can be referred to but cannot be updated is added to the volume in the storage system A. Then, if the volume is a volume to which the attribute to the effect that data can be referred to but cannot be updated is added, such attribute is added to the volume in the storage system B.
    Type: Application
    Filed: July 6, 2004
    Publication date: December 1, 2005
    Inventors: Yusuke Nonaka, Naoto Matsunami, Akira Nishimoto, Yoichi Mizuno
  • Publication number: 20050262300
    Abstract: To provide a disk array system which particularly enables the use of a WORM function when the disk array system uses RAID. When receiving a write request from a computer (100), it is judged whether or not a writing of write data from the computer is possible, based on a content indicated by write inhibition information. If the writing is possible, the guarantee code of the transferred data is generated, the write inhibition information indicating that a region in which the data is stored is not writable is generated, and the generated write inhibition information is stored in the guarantee code, the guarantee code storing the write inhibition information is assigned to the region in which the data received from the computer (100) is stored, and the data to which the guarantee code storing the write inhibition information is assigned is stored in a cache memory (230) and/or a disk drive (270). If the write data from the computer (100) is not writable, it is informed to the computer (100).
    Type: Application
    Filed: August 4, 2004
    Publication date: November 24, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Akihiro Mannen, Naoto Matsunami, Akira Nishimoto, Yusuki Nonaka
  • Publication number: 20050251620
    Abstract: The storage system includes a plurality of storage nodes and a control device coupling unit. Each of the storage nodes includes at least one storage device configured to store data and at least one control device configured to control input and output of data for the storage device. The control device coupling unit is configured to connect the control devices without using an access path between the control device and a host computer connected to the storage system. The control devices connected by the control device coupling unit are included in mutually different storage nodes.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 10, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Naoto Matsunami, Tetsuya Shirogane, Naoko Iwami, Kenta Shiga, Akira Nishimoto
  • Publication number: 20050240854
    Abstract: A storage system includes a group of storage devices which include back-up devices configured to assure appropriate response time. When a data request from a host computer arrives, and the number of failed devices has changed as shown by a device state management table, a determination is made regarding the number of devices from which to read data. This determination is made based on an indication of redundancy which indicates how many of the disk devices are allowed to be in a failed state at the time of data reading. Typically, the indication of redundancy is determined by the sum of the number of failed devices and a predetermined number. The determined number of devices are selected in accordance with a selection factor, and a selection result is written into a disk management table. Then, the reading process is executed with respect to the target disk devices.
    Type: Application
    Filed: May 28, 2004
    Publication date: October 27, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Yutaka Nakagawa, Akira Nishimoto, Naoto Matsunami
  • Publication number: 20050223167
    Abstract: A diskarray system includes a disk device for storing write data received from a computer, a cache memory, and a controller for controlling input and output of data to and from the disk device. The controller determines whether or not the write data is already written in a storage area of the diskarray system to be written specified by a write command received from the computer. When the write data for the storage area to be written is not written yet in the diskarray system, the controller receives the write data according to the write command and stores the received data in the cache memory.
    Type: Application
    Filed: June 3, 2004
    Publication date: October 6, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Akira Nishimoto, Naoto Matsunami, Ikuya Yagisawa
  • Publication number: 20050216659
    Abstract: To provide a storage system which enables usage of a greater volume of cache than that of a cache memory provided to a disk array control unit, including a first disk array control unit, a second disk array control unit, a plurality of disks, and a disk array control unit communication path between a first data transfer control unit and a second data transfer control unit, wherein the first data transfer control unit selectively sets either a first path through a first host input/output control unit, the first data transfer control unit, and a first disk input/output control unit, or a second path through the first host input/output control unit, the first data transfer control unit, the disk array control unit communication path, the second data transfer control unit, and a second disk input/output control unit, and then processes a data input/output request from a host
    Type: Application
    Filed: June 7, 2004
    Publication date: September 29, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Junji Ogawa, Naoto Matsunami, Akira Nishimoto, Yoichi Mizuno
  • Publication number: 20050210188
    Abstract: It is an object to achieve higher performance of input/output processing in a storage system. In a disk controller of a storage system having disk devices and a disk controller that controls input/output of data to/from the disk devices and that accepts requests from a superordinate device, there are provided a memory, a superordinate IF and a subordinate IF (1201), for the exclusive use of each MPU.
    Type: Application
    Filed: May 18, 2004
    Publication date: September 22, 2005
    Inventors: Yoichi Mizuno, Naoto Matsunami, Akira Nishimoto
  • Publication number: 20050172043
    Abstract: A hybrid-type storage system having both SAN and NAS interfaces can be implemented by simple hardware capable of carrying out a SAN function independently of a NAS function and a NAS load. To be more specific, a controller of the storage system comprises a NAS controller for accepting an I/O command issued for a file unit and a SAN controller for accepting an I/O command issued for a block unit. The NAS controller converts an I/O command issued for a file unit into an I/O command issued for a block unit, and transfers the I/O command issued for a block unit to the SAN controller. The SAN controller makes an access to data stored in a disk apparatus in accordance with an I/O command received from the SAN or from the NAS controller as a command issued for a block unit. The NAS and SAN controllers are capable of operating independently of each other.
    Type: Application
    Filed: March 22, 2004
    Publication date: August 4, 2005
    Inventors: Yusuke Nonaka, Naoto Matsunami, Ikuya Yagisawa, Akira Nishimoto
  • Publication number: 20040010073
    Abstract: A polyester resin composition for profile extrusion molding comprising an amorphous polyester, at least one component selected from the group consisting of a crystalline polyester and a nucleating agent, and optionally a reactive compound; a polyester resin composition for profile extrusion molding comprising a polyester resin, and a reactive compound having a weight average molecular weight of 200 to 500,000; and a profile shape comprising a resin having a reduced viscosity ratio of 1.01 to 3.00, a reduced viscosity ratio being a ratio of a reduced viscosity of a resin after molding to that of a resin before molding. They do not suffer from sagging in the molding process, they improve the shape accuracy at corners and edges of profile shapes from a die to a sizing step and also resistance to whitening on bending in transparent products, and can provide profile shapes having good solvent resistance and detergent resistance.
    Type: Application
    Filed: February 13, 2003
    Publication date: January 15, 2004
    Inventors: Kenji Shiga, Akira Nishimoto, Osamu Iritani, Kazunori Komatsu, Mitsuo Nishida
  • Patent number: 6560676
    Abstract: A cache memory system employing a set associative system with a plurality of ways which can store data having a same set address is disclosed. The cache memory system includes a replace circuit for controlling replacement of data stored in a cache memory according to a predetermined replace algorithm, and a limiting circuit for limiting ways to which blocks to be replaced by the replace circuit belong. The limiting circuit receives a mode signal specifying whether replace ways should be limited. The limiting circuit limits ways to be replaced when the mode signal indicates that the limitation should be performed and an instruction to be executed is a prefetch instruction.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: May 6, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Akira Nishimoto, Eiki Kamada, Akira Hirono