Abstract: In a high withstand voltage transistor of a LOCOS offset drain type having a buried layer, a plurality of stripe-shaped diffusion layers are formed below a diffusion layer ranging from an offset layer to a drain layer and a portion between the drain region and the buried layer is depleted completely; thus, a withstand voltage between the drain region and the buried layer is improved. By the formation of the stripe-shaped diffusion layers, the drain region becomes widened; thus, on-resistance is reduced. Further, the buried layer is made high in concentration so as to sufficiently suppress an operation of a parasitic bipolar transistor.

Abstract: This invention aims at providing an inexpensive semiconductor device having a parasitic diode and lowering an hfe of a parasitic PNP transistor and a manufacturing method thereof. Such semiconductor device includes a P-type silicon substrate and a gate electrode formed above the P-type silicon substrate. The P-type silicon substrate includes an N-type well layer, an N-type buried layer, a P-type body layer, an N-type source layer formed in the P-type body layer, and a drain contact layer formed in the N-type well layer. The P-type body layer and the N-type source layer are formed by self alignment that uses the gate electrode as a mask. The N-type drain contact layer is formed opposite the N-type source layer across the P-type body layer formed below the gate electrode. The N-type buried layer is formed below the P-type body layer.

Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.

Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.

Abstract: In a high withstand voltage transistor of a LOCOS offset drain type having a buried layer, a plurality of stripe-shaped diffusion layers are formed below a diffusion layer ranging from an offset layer to a drain layer and a portion between the drain region and the buried layer is depleted completely; thus, a withstand voltage between the drain region and the buried layer is improved. By the formation of the stripe-shaped diffusion layers, the drain region becomes widened; thus, on-resistance is reduced. Further, the buried layer is made high in concentration so as to sufficiently suppress an operation of a parasitic bipolar transistor.

Abstract: This invention aims at providing an inexpensive semiconductor device having a parasitic diode and lowering the hfe of a parasitic PNP transistor and a manufacture method thereof. Such semiconductor device includes a P-type silicon substrate 1 and a gate electrode 5 formed above the P-type silicon substrate 1. The P-type silicon substrate 1 includes an N-type well layer 2, an N-type buried layer 3, a P-type body layer 6, an N-type source layer 7 formed in the P-type body layer 6, and a drain contact layer 8 formed in the N-type well layer 2. The P-type body layer 6 and the N-type source layer 7 are formed by self alignment that uses the gate electrode 5 as a mask. The N-type drain contact layer 8 is formed opposite the N-type source layer 7 across the P-type body layer 6 formed below the gate electrode 5. The N-type buried layer 3 is formed below the P-type body layer 6.