Patents by Inventor Akira Ohta
Akira Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6563750Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: GrantFiled: April 30, 2002Date of Patent: May 13, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
-
Publication number: 20020186088Abstract: A high-frequency amplifier in a power amplifier module includes, on a substrate on which the amplifier is formed, first- and second-stage amplifiers for receiving and amplifying an input signal, a harmonic processing circuit for matching of harmonics included in an output signal from the second-stage amplifier, and a low-pass filter receiving an output from the harmonic processing circuit to selectively pass a signal to be supplied to a non-reciprocal circuit element using a predetermined frequency as a cutoff frequency.Type: ApplicationFiled: November 15, 2001Publication date: December 12, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Akira Ohta, Akira Inoue
-
Publication number: 20020182711Abstract: The invention provides an enzymatic unhairing agent for use in an unhairing step in tanning for producing leather comprising an alkaline protease as an active component; a treatment solution comprising a pH-adjusting agent and the enzymatic unhairing agent; a method for enzymatic unhairing treatment in tanning for producing leather comprising contacting the treatment solution with a raw hide or skin; and a leather thus produced. According to the invention, it is attained markedly reduction of the pollution load in the unhairing waste water and leather and recovered hairs both of good quality can be obtained.Type: ApplicationFiled: June 3, 2002Publication date: December 5, 2002Inventors: Yasuhiro Shimizu, Sugiyama Atsushi, Akira Ohta
-
Publication number: 20020118587Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: ApplicationFiled: April 30, 2002Publication date: August 29, 2002Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
-
Publication number: 20020063603Abstract: A high frequency power amplifier that can improve an efficiency of an operation of a transistor without limiting any input-side higher harmonic load of an impedance matching circuit to a short-circuit load, and can increase a quantity of reflection of higher harmonics. By adjusting line lengths L1 to L5 and line widths W1 to W5 of the signal lines 1 to 5, a 2nd higher harmonic can be adjusted to be an open load (a reflected phase angle of &Ggr;in: 0-90°, the quantity of reflection: 0.6-1.0), and a 3rd higher harmonic is adjusted to be a short-circuit load (the reflected phase angle of &Ggr;in:110-270°, the quantity of reflection: 0.6-1.0). By this optimization of an input-side higher harmonic load of the impedance matching circuit, an efficiency of transistor operation can be improved.Type: ApplicationFiled: June 18, 2001Publication date: May 30, 2002Inventors: Seiki Gotou, Akira Ohta
-
Patent number: 6388941Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: GrantFiled: July 13, 2001Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Hitachi, ULSI Systems Co., Ltd.Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
-
Patent number: 6376581Abstract: A cement dispersant having excellent ability to prevent slump loss and high water-reducing property which comprises a polycarboxylic acid type polymer having a specific molecular weight distribution, a method for the production thereof, and a cement composition using the dispersant are provided. The cement dispersant comprises as a main component thereof a polycarboxylic acid type polymer (A), having a weight average molecular weight in the range of 10,000 to 500,000 in terms of polyethylene glycol determined by gel permeation chromatography, and having a value determined by subtracting the peak top molecular weight from the weight average molecular weight in the range of 0 to 8,000.Type: GrantFiled: November 1, 2000Date of Patent: April 23, 2002Assignee: MBT Holding AGInventors: Yoshio Tanaka, Akira Ohta, Tsuyoshi Hirata, Toru Uno, Tsutomu Yuasa, Hideyuki Tahara
-
Publication number: 20020008595Abstract: A radio-frequency composite element 10 is formed by an element substrate carrying a high-efficiency amplifier 14, a transmission line 16 and an isolator 12, the amplifier 14 being made of a semiconductor element mounted on a multilayer substrate and enveloped by a cover, and the transmission line 16 furnished on the element substrate 18 connecting an output terminal of the high-efficiency amplifier with an input terminal of the isolator, so that the components make up an integrally formed composite element.Type: ApplicationFiled: December 5, 2000Publication date: January 24, 2002Inventors: Akira Ohta, Akira Inoue
-
Patent number: 6187841Abstract: A cement dispersant having excellent ability to prevent slump loss and high water-reducing property which comprises a polycarboxylic acid type polymer having a specific molecular weight distribution, a method for the production thereof, and a cement composition using the dispersant are provided. The cement dispersant comprises as a main component thereof a polycarboxylic acid type polymer (A), having a weight average molecular weight in the range of 10,000 to 500,000 in terms of polyethylene glycol determined by gel permeation chromatography, and having a value determined by subtracting the peak top molecular weight from the weight average molecular weight in the range of 0 to 8,000.Type: GrantFiled: July 12, 1996Date of Patent: February 13, 2001Assignee: MBT Holding AGInventors: Yoshio Tanaka, Akira Ohta, Tsuyoshi Hirata, Toru Uno, Tsutomu Yuasa, Hideyuki Tahara
-
Patent number: 6177841Abstract: A high frequency power amplifier with reduced power loss and improved power amplification efficiency has an output matching circuit providing an open circuit to a second harmonic and a short circuit to a third harmonic of a high frequency signal. This is accomplished by, for example, adjusting lengths of a drain bias line and a plurality of signal lines so that the phase of S parameter S11 (input reflection coefficient) to the second harmonic is from −80° to 140°, and the phase of S parameter S11 to the third harmonic is from 160° to 220°. The line length of each line in an input matching circuit is also adjusted so that the phase of S parameter S22 (output reflection coefficient) at the fundamental frequency is between +5° to −75°.Type: GrantFiled: February 26, 1999Date of Patent: January 23, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Ohta, Akira Inoue, Tetsuya Heima
-
Patent number: 5880182Abstract: An admixture for decreasing the water demand of cementitious compositions such as concrete consists of(a) from 75-25% by weight of a water-reducing agent whose major component is a polycarboxylate; and(b) from 25-75% by weight of at least one saccharide component selected from hydrogenated saccharides and polyhydric alcohol adducts of saccharides.The saccaride component is preferably a hydrogenated polysaccharide with a molecular weight distribution as follows:(i) 70-30% by weight (on total weight of hydrogenated saccharides) have molecular weights in the range 180-300;(ii) 30-70% by weight have molecular weights of from 300 up to 4,000; and(iii) 30% by weight maximum have molecular weights of 4,000 and over.Type: GrantFiled: February 18, 1997Date of Patent: March 9, 1999Assignee: MBT Holding AGInventors: Yoshikazu Minomiya, Akira Ohta, Minoru Yaguchi
-
Patent number: 5859554Abstract: A variable delay circuit that delays an input signal for a desired time and outputs the delayed signal includes N (N is an integer of 2 or more) load transistors and N control transistors for controlling the load transistors respectively connected in pairs in series to form N load transistor pairs. The load transistor pairs are connected in parallel to form a load transistor group. A switching transistor that is turned on or off according to an input signal input to a gate, and the load transistor group are connected in series between first and second power supplies. The input signal is delayed according to control signals that are respectively input to the control transistors, and a delayed signal is output from a connection node of the load transistor group and the switching transistor. Since no selector is required, a delay circuit operation due to differences in delay times between paths in a selector is avoided, thereby obtaining a variable delay circuit having minute resolution and a good yield.Type: GrantFiled: December 23, 1996Date of Patent: January 12, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Norio Higashisaka, Akira Ohta, Tetsuya Heima
-
Patent number: 5834960Abstract: A semiconductor device includes an input terminal and an output terminal; a delay circuit including N (N=integer) unit delay circuits connected in series between the input terminal and the output terminal, earn unit delay circuit including first and second two-input NOR or NAND circuits connected in series, the second two-input NOR or NAND circuit being nearer to the output terminal than the first two-input NOR or NAND circuit, a first input of each first two-input NOR or NAND circuit being connected to the input terminal, and an output of each first two-input NOR or NAND circuit being connected to a first input of the second two-input NOR or NAND circuit of each unit delay circuit; and a control circuit outputting individual control signals, each control signal being applied to a respective second input of the second two-input NOR or NAND circuit included in each unit delay circuit, wherein delay time in signal transmission from the input terminal to the output terminal varies in response to the control signType: GrantFiled: June 23, 1997Date of Patent: November 10, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Heima, Norio Higashisaka, Akira Ohta
-
Patent number: 5821793Abstract: A variable delay circuit including an input terminal to which a signal to be delayed is input, a delay gate connected to the input terminal, a logical gate to which an input to the delay gate and an output from the delay gate are input and which forms a delayed signal, and an output terminal outputting the delayed signal formed by the logical gate. A control signal for controlling the delay gate is input to the delay gate.Type: GrantFiled: August 12, 1996Date of Patent: October 13, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Ohta, Norio Higashisaka, Tetsuya Heima
-
Patent number: 5780129Abstract: There is provided a multi-layer blow-molded article wherein in a multi-layer marginal-wall region formed of a plurality of layers, a convexly crooked portion projecting generally convexly from inside to outside is so formed that the molding shrinkage factor of a resin for use in a more outer layer is larger than that of a resin for use in a more inner layer, and a concavely crooked portion denting generally concavely from outside to inside is so formed that the molding shrinkage factor of a resin for use in a more outer layer is smaller than that of a resin for use in a more inner layer; and all the layers of the molded article are fittingly secured to each other by means of a clamping force resulting from the difference in molding shrinkage factors of the resins constituting the layers and/or portions defined in a circumferential direction in the multi-layer marginal-wall region.Type: GrantFiled: June 28, 1996Date of Patent: July 14, 1998Assignees: Nippon Steel Chemical Co., Ltd., Nippon Steel CorporationInventor: Akira Ohta
-
Patent number: 5718927Abstract: An apparatus for manufacturing multilayer hollow articles having sections different from one another in respect to the kinds of resins, number of layers, and thickness of layers along the circumference in the horizontal section of an article with the narrowest of the sections in any one of the resin layers extending in a specified width along the longitudinal wall of an article and being capable of satisfying the sectional performance requirements. An apparatus is provided for manufacturing multilayer hollow articles with the wall thickness ratio of resin layers in each section varying along the longitudinal wall of an article or those with the sectional width in each resin layer varying along the longitudinal wall of an article. Hollow articles molded by the apparatus of this invention are particularly useful for automotive bumpers, the seats and backs of chairs, and boiler-room doors.Type: GrantFiled: May 15, 1995Date of Patent: February 17, 1998Assignees: Nippon Steel Chemical Co., Ltd., Nippon Steel CorporationInventors: Akira Ohta, Kohsei Kushima, Satoshi Furuki
-
Patent number: 5716447Abstract: A cement pumpability-enhancing additive which comprises polyethylene glycol and diethylene glycol monobutyl ether and/or a derivative thereof, and optionally polysaccharide. The additive is especially useful for high-strength, high-flow concretes for use in construction.Type: GrantFiled: August 1, 1997Date of Patent: February 10, 1998Assignee: MBT Holding AGInventors: Shigemi Matsuo, Akira Ohta, Tadashi Tsuchitani, Minoru Ueda
-
Patent number: 5682114Abstract: In a variable delay circuit for delaying an input signal by a variable delay time from a rising edge or a falling edge of the input signal to a rising edge or a falling edge of an output signal in a digital circuit, a data signal input terminal; a first signal input terminal to which a low-level signal of a logic gate is applied; n selector circuits (n=integer larger than 0) selecting either the signal at the data signal input terminal or the signal at the first signal input terminal in response to signals applied to first selector signal input terminals; and an (n+1)-input NOR circuit to which the signal at the data signal input terminal and output signals from the selector circuits are applied. In this variable delay circuit, a delay time shorter than the delay time of a single-stage buffer circuit can be controlled using only digital circuits.Type: GrantFiled: October 19, 1995Date of Patent: October 28, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Akira Ohta
-
Patent number: 5667748Abstract: This invention provides a blow molding process for manufacturing multilayer hollow articles having sections different from one another in respect to the kind of resins, number of layers, and thickness of layers along the circumference in the horizontal section of an article with the narrowest of the sections in any one of the resin layers extending in a specified width along the longitudinal wall of an article and being capable of satisfying the sectional performance requirements, an apparatus, and said hollow articles. It also provides a process for manufacturing multilayer hollow articles with the wall thickness ratio of resin layers in each section varying along the longitudinal wall of an article or those with the sectional width in each resin layer varying along the longitudinal wall of an article, an apparatus, and said hollow articles.Type: GrantFiled: May 15, 1995Date of Patent: September 16, 1997Assignees: Nippon Steel Chemical Co., Ltd., Nippon Steel CorporationInventors: Akira Ohta, Kohsei Kushima, Satoshi Furuki
-
Patent number: 5668491Abstract: A variable delay circuit includes a gate chain of first to n-th delay gates (n is an integer larger than 2) connected in series to each other via delay gate wirings having respective wiring lengths, the first delay gate receiving an input signal for delay; first to n-th separator gates to which the outputs of the first to n-th delay gates are input, respectively; first to n-th separator gate wirings having wiring lengths successively shortened from the first to n-th separator gate, first ends respectively connected to the first to n-th separator gates, and second ends connected to an n:1 selector, for selecting one of the outputs of the first to n-th separator gates in according with a select signal, and a select signal generating circuit for controlling the n:1 selector. The variable delay circuit has no loss of resolution due to parasitic capacitance of the delay gate wirings.Type: GrantFiled: January 11, 1996Date of Patent: September 16, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Norio Higashisaka, Akira Ohta