Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.

Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.

Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.

Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.

Abstract: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Abstract: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Abstract: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Abstract: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Abstract: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Abstract: A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.

Abstract: A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.

Abstract: There is provided a testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, the divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of the contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these bocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Thereby, each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.