Abstract: A first series of filter coefficients stored in a memory itself corresponds to a given filter characteristic such as a given high cutoff frequency. A second series of filter coefficients is generated by performing an interpolation process on the first series of filter coefficients. At that time, the contents, such as interpolation coefficients, of the interpolation process are varied in correspondence to a desired filter characteristic to be achieved, so that the interpolation process generates a second series of filter coefficients according to an impulse response characteristic that is obtained as a consequence of expanding or compressing, in a time-axis direction, an impulse response characteristic represented by the given first series of the filter coefficients. Thus, by the interpolation process, there is produced such a second series of filter coefficients that achieves a different filter characteristic (e.g., different high cutoff frequency).

Abstract: A digital signal processor (DSP) is disclosed which is capable of starting a new arithmetic operation even when results of completed arithmetic operations cannot be written into accumulators because they already contain results. The DSP includes an arithmetic operation unit, a bus, at least one accumulator and a bypass device. The bus transfers data to be processed by the arithmetic operation unit in addition to the results of arithmetic processing performed by the arithmetic operation unit. The at least one accumulator holds the results of arithmetic processing and delivers the results to the bus. The bypass device may contain a delay element that delays delivery of the results to the bus for the same length of time that it would take for the results to be delivered to the bus via the at least one accumulator.

Abstract: An A/D conversion apparatus is provided, which is capable of securing a wide dynamic range of A/D conversion with a simple construction through suitably switching the input gain of the input analog signal between predetermined levels. An input gain control device controls gain of an input signal based on a control signal. A &Dgr;&Sgr; modulator carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit. A detecting device detects a peak value of the input signal based on the data of one bit. A gain control device generates the control signal based on the peak value detected by the detecting device in a manner such that the input signal having the gain thereof controlled falls within a predetermined range.

Abstract: An electro-coagulation printer uses an electrode control unit to drive electrodes which are aligned in proximity to a rotation drum having a conductive ink film on its surface. The electrodes are respectively electrified to partially coagulate the conductive ink film to form ink dots on the surface of the rotation drum, so that the ink dots are transferred onto a paper. Herein, the electrode control unit receives print data from a host device by way of an interface. Gradation data representing gradation values for one line of the electrodes are created based on the print data and are output in a serial manner. The serial gradation data are converted to parallel data corresponding to the gradation values, which are held and controlled in output timing. Based on the gradation values, pulse signals are generated to drive the electrodes respectively.

Abstract: There is provided a digital signal processor. A bus transfers data to be processed by an arithmetic operation unit and results of arithmetic processing by the arithmetic operation unit. At least one accumulator holds the results of the arithmetic processing by the arithmetic operation unit and delivers the results to the bus. A bypass device delivers the results by bypassing the at least one accumulator.

Abstract: There is provided a digital signal processor. A bus transfers data to be processed by an arithmetic operation unit and results of arithmetic processing by the arithmetic operation unit. At least one accumulator holds the results of the arithmetic processing by the arithmetic operation unit and delivers the results to the bus. A bypass device delivers the results by bypassing the at least one accumulator.

Abstract: There is provided a digital signal processor. A bus transfers data to be processed by an arithmetic operation unit and results of arithmetic processing by the arithmetic operation unit. At least one accumulator holds the results of the arithmetic processing by the arithmetic operation unit and delivers the results to the bus. A bypass device delivers the results by bypassing the at least one accumulator.

Abstract: A voice synthesis system is fundamentally configured by a sound-source model, which simulates human voices and the like, and a voice-path model which simulates properties of voice paths between vocal cords and lips. The sound-source model is embodied by a code book which stores a plurality of code words, representative of waveform patterns, with respect to each of the voices. Each of the code words is selected by an information index. The voice-path model is embodied by a full-pole synthesis filter whose characteristic curve provides multiple poles, each of which is represented by polar coordinates. There is further provided a pitch filter and an all-pass filter. Data representative of the code word selected is supplied to the pitch filter, in which a first delay time, set by a number of delay-time units, is imparted to the data. Then, the all-pass filter imparts a second delay time, which is smaller than the delay-time unit, to the data in response to pitch-variation information.

Abstract: A mixing circuit for synthesizing plural .DELTA..SIGMA. modulated data generated simultaneously with a bit rate F to single mixed data includes a slot determining section for dividing time length corresponding to 1-bit period of the .DELTA..SIGMA. modulated data into a number N which is of the same number as the plural .DELTA..SIGMA. modulated data, and a time division multiplex section for assigning in order the plural .DELTA..SIGMA. modulated data to the 1-bit period at a bit rate N*F on a time shared basis. The obtained mixed data can be converted to linear PCM data with a single decimation circuit. By increasing the bit rate of the mixed data by N times the bit rate F of the .DELTA..SIGMA. modulated data, a total gain can be maintained at a constant value irrespective of a change in the number of data to be synthesized.

Abstract: A sine-wave generator circuit is provided to generate data representative of a sine wave by using a ROM which stores sine-wave data of only a selected phase region between 0 and .pi./2, for example. The circuit receives input phase data which are represented by twos complements and whose low-order bits are used as address data for the ROM; and each bit of the input phase data has a specific weight factor. When reading out data from the ROM, a normal order or a reverse order for the address data is designated in accordance with high-order bits of the input phase data, so that data representative of other phase regions are generated based on output of the ROM. Then, phase adjustment is performed on the data in accordance with the high-order bits. The data stored in the ROM has certain offset in advance in order to regenerate a sine wave accurately; however, the offset causes an error in output of the ROM.

Abstract: A modulator-demodulator (i.e., modem) permits a personal computer and the like to receive and transmit data in digital format across voice-oriented communications links such as telephone lines. A full-duplex-type modem employs a decoding device decoding the data which are subjected to convolution-encoding operation and amplitude-phase modulation. That data is subjected to amplitude-phase demodulation at first: and then, it is subjected to viterbi decoding by which an error correction is carried out. In the amplitude-phase demodulation, an amplitude-phase plane is employed and is divided into a plurality of areas in accordance with an arrangement of signal-placing points which is used by the amplitude-phase modulation. When receiving the data, a certain receiving point is defined. Then, one of the areas to which the receiving point belongs is determined; and its area information is produced.

Abstract: A data conversion apparatus for a facsimile system converts a first digital data composed of a sequence of primary values sampled at a first frequency, into a second digital data composed of a sequence of secondary values sampled at a second frequency different from the first frequency. The apparatus is provided with a sampling frequency conversion unit operative before and after every sampling point timed by the second frequency for sampling a pair of preceding and succeeding primary values and for counting respective time differences from the sampling point to the preceding and succeeding primary values. The sampling frequency conversion unit further calculates a secondary value at every sampling point by linear interpolation of each pair of the sampled preceding and succeeding primary values according to the counted time differences to thereby produce the second digital data.

Abstract: A full-duplex-type modem employs a decoding device decoding the data which are subjected to convolution-encoding operation and amplitude-phase modulation. That data is subjected to amplitude-phase demodulation at first; and then, it is subjected to viterbi decoding by which an error correction is carried out. In the amplitude-phase demodulation, an amplitude-phase plane is employed and is divided into a plurality of areas in accordance with an arrangement of signal-placing points which is used by the amplitude-phase modulation. When receiving the data, a certain receiving point is defined. Then, one of the areas to which the receiving point belongs is determined; and its area information is produced. A plurality of candidate paths are determined by referring to the signal-placing points which are arranged around the area to which the receiving point belongs.

Abstract: A method and device for correcting an error in digital data in which data of one frame consists of bit assignment data and plural data each consisting of a bit number assigned by the bit assignment data comprises a step of substituting the plural data by noise data when an error has occurred in the bit assignment data. In one aspect of the invention, a method for correcting an error in digital data in which data of one frame consists of bit assignment data and plural data each consisting of exponential data assigned by the bit assignment data and mantissa data of a number of bits assigned by the bit assignment data, comprising a step of correcting the exponential data on the basis of a preceding frame or on the basis of both preceding and subsequent frame and substituting the mantissa data by noise data when an error has occurred in the bit assignment data. The noise data may be band-limited noise.

Abstract: First two dimensional plane is defined by phase of modulated signal and first vector corresponding to first signal point to be decided is defined. Then, first inner product by the first vector and second vector corresponding to last decided signal point is made and the second vector is transformed into third vector which is ninety degrees advanced. Next, second inner product of the first vector and third vector is made and the region of the first signal is decided in the two dimensional plane in accordance with the first and second inner product.

Abstract: A FM demodulation circuit contains an analog-to-digital converter which converts an inputted frequency-modulated (FM) signal into a digital signal of one bit at a timing based on the predetermined clock signal and a differentiation circuit which differentiates the digital signal to thereby output a pulse train whose pulse density is in proportion to a frequency of the inputted FM signal. When the pulse train is supplied to a low-pass filter, the pulse train is converted into an analog signal, which is outputted as a demodulated signal. When the pulse train is supplied to a decimation circuit which includes a weight function generating portion and an accumulator, weighted function values are sequentially accumulated based on the level of the pulse train in the predetermined period so that the demodulated signal can be obtained in the form of a linear pulse code modulated (linear PCM) signal.